Hamilton Sundstrand Corporation

Ashish Vijay

Anil Prasad Josyula

Somasekhar Valleru

Sesh Mohan Rao

Rajeeva Gopala Krishna

Anitha Thangavel

Rajesh Madathikandam

Rajeeva Krishna

Harish Venkatesha

Sundaram Kaliyugavaratharajan

Stephen Potter

Robin David Hill

Manish Kumar

Nageswara Rao Kalluri

Sridhar Katakam

David Frederick Brookes

Shardul Shrinivas Bapat

Kannan Thiagarajan

Sangameswaran Kamanathan

Rajagopal Srinivasan

Vipul Kohli

Divya Nagaraju

A bus controller-based page memory programmable logic device (PLD) architecture includes a plurality of PLD modules and a bus controller in signal communication with the plurality of PLD modules via a universal bus interface. Each PLD module include a PLD memory unit configured to store first data. The bus controller includes bus memory unit configured to store second data and includes a bus controller engine configured to sequentially execute a set of bus controller instructions. One or both of the first data and the second data is transferred between the bus controller and a target PLD module among the plurality of PLD modules in response to sequentially executing the set of bus controller instructions.

Scalable and modular bus controller including page memory PLD architecture

A microprocessor-PLD hybrid architecture includes an IPC microprocessor and a PLD in signal communication with the IPC microprocessor via an IPC interface. The IPC microprocessor outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules that store data and a bus controller. The bus controller communicates with the plurality of PLD modules via a plurality of PLD interfaces and is configured to sequentially execute a set of bus controller instructions. The bus controller reads data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the data to the IPC microprocessor. The bus controller receives data from the IPC microprocessor and stores the data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.

Hybrid microprocessor and programmable logic device (PLD)-based architecture including inter processor communication

A hoist application system is provided. The hoist application system includes a motor drive unit, which is receptive of a final duty command and which drives a motor in accordance with the final duty command, a closed-loop control unit configured to generate a closed-loop duty command, an open-loop control unit configured to generate an open-loop duty command and a switch logic unit. The switch logic unit is receptive of direct current (DC) system information, the closed-loop duty command and the open-loop duty command, and is configured to generate the final duty command from one of the closed-loop duty command and the open-loop duty command based on the DC system information.

Current limit strategy for hoist application

A motor temperature control system for an electric aircraft is provided. The motor temperature control system includes an electric motor, circuitry and a thermoelectric generator (TEG). The TEG is disposed in thermal communication with the electric motor. The TEG is electrically coupled to the circuitry such that heat generated by the electric motor is converted by the TEG to electrical energy that generates a voltage drop across the circuitry.

Sensor-less temperature monitoring

A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.

Timer-based resolver integral demodulation

System and methods for motor drive electronics are provided. Aspects include receiving, by a controller on a motor driver electronics (MDE) component, voltage data associated with a thermoelectric generator, wherein the MDE component is configured to operate an electric motor, and wherein the MDE component comprises a power card including one or more components, determining a temperature reading based on the voltage data, enacting an action associated with the MDE component based at least in part on the temperature reading.

Motor drive electronics using thermoelectric material

An intelligent architecture system is provided. The intelligent architecture system includes an input line, an output line and an intelligent architecture operably interposed between the input line and the output line. The intelligent architecture is configured to control a voltage of the output line in accordance with a voltage of the input line.

Intelligent architecture for actuator motor drive powered from wide-input high-voltage direct current

Examples described herein provide a method that includes storing, in a first buffer associated with a first ADC of a DSP, resolver sine values collected from first, second, and third resolvers. The method further includes storing, in a second buffer associated with a second ADC of the DSP, resolver cosine values collected from the first, second, and third resolvers. The method further includes storing, in a third buffer associated with a third ADC of the DSP, resolver excitation values collected from the first, second, and third resolvers. The method further includes determining a midpoint value of the resolver excitation values, determining a sine amplitude based at least in part on the resolver sine values and the midpoint value, and determining a cosine amplitude based at least in part on the resolver sine values and the midpoint value. The method further includes identifying a quadrant of a resolver position.

Resolver integral demodulation using zero crossing points

A system for controlling a motor with a plurality of motor control functions including at least a current control loop and a velocity control loop. The system includes one of a hybrid Digital Signal Processor (DSP)-Field Programmable Gate Array (FPGA) architecture having an integral DSP and an integral FPGA or a System on a Chip (SoC) architecture having a Microcontroller Sub-System (MSS) and an FPGA fabric. The current control loop function is assigned to the integral FPGA for the hybrid DSP-FPGA architecture, and at least the velocity control loop function is assigned to the DSP the hybrid DSP-FPGA architecture. Alternatively, the current control loop function is assigned the FPGA fabric of the SoC architecture, and at least the velocity control loop function is assigned to the MSS of the SoC architecture.

Optimized allocation of functions in hybrid motor controller implementations

Provided are embodiments for a system including an adaptive controller, wherein the system includes a hydraulic actuator including a fluid medium, and a sensor that is disposed on the hydraulic actuator, wherein the sensor is configured to obtain sensor data of the actuator. The system also includes a processor configured to calculate an ultrasonic velocity in the fluid medium using the sensor data, wherein the processor is further configured to determine a temperature of the fluid medium based at least in part on the calculated velocity, and a controller coupled to the actuator, wherein the controller is configured to control the actuator based at least in part on the calculated velocity and determined temperature. Also provided are embodiments for a method for operating the adaptive controller.

Performance enhancement of controllers for varying temperature conditions in hydraulic actuators

A method of performing a built in test on a watchdog circuit including a watchdog timer includes: initiating the built in test with a processor being monitored by the watchdog circuit, wherein initiating includes enabling a watchdog circuit built in test reset inhibit circuit (WD BIT reset inhibit circuit) connected between an output of an active watchdog integrated reset circuit connected to the processor and a reset input of the processor; and ceasing to provide a strobe signal to the active watchdog integrated reset circuit that resets a watchdog counter in the active watchdog integrated reset circuit, the active watchdog integrated reset circuit causing a reset of the processor via its output when the watchdog counter expires by providing a signal to a reset input of the processor.

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Rajasthan, India

Ashish Vijay