Intel Corporation

Other

Tahoe Research, Ltd.

Ashish V Choubal

Inder M Sodhi

Arvind Raman

Sanjeev S Jahagirdar

Krishnakanth Venkata Sistla

Alexander Gendler

Ken Drottar

Rabiul Islam

Vishram Sarurkar

Yun-Han Chen

Ryan Donovan Wells

Satish K Damaraju

Efraim Rotem

Ankush Varma

Nir Rosenzweig

Belliappa Manavattira Kuttanna

Bruce L Fleming

Jason W Brandt

Andrew J Herdrich

Michael Mishaeli

Arvind Mandhani

Andrew D Henroid

Ajaya V Durg

Kalyan Muthukumar

Christopher T Foulds

Sundar Ramani

Samudyatha Chakki

Bret L Toll

Eliezer Weissmann

Muhammad M Khellah

Alon Naveh

Dheeraj R Subbareddy

Eugene Gorbatov

Stephen Anthony Fischer

Rajesh Bhikhubhai Patel

Vivek Garg

David A Koufaty

Dean A Mulla

Hemal Vinodchandra Shah

Charles Augustine

Ganapati Srinivasa

Lance E Hacking

Sanjoy K Mondal

Harlan Titus Beverly

Scott D Hahn

Hisham Shafi

Paolo L Narvaez

Rinat Rappoport

Gary Tsao

Gaurav Khanna

Mishali Naik

Paul Brett

Abirami Prabhakaran

Oron Lenz

Feroze Merchant

Madhu Gumma

Sanjeev S Sahagirdar

Tsung-Yuan Charles Tai

Ren Wang

Ravishankar Iyer

Blaise B Fanning

Alexander W Min

Avinash N Ananthakrishnan

Jr-Shian Tsai

Russell Jerome Fenger

Tse-Yu Yeh

Eric J DeHaemer

Rameshkumar G Illikkal

Kenneth D Shoemaker

Mesut A Ergin

Zeev Offen

Larisa Novakovsky

James Steven Burns

Guy G Sotomayor

Jaideep Moses

Ramana V Rachakonda

Johan G Van De Groenendaal

Sadagopan Srinivasan

Mircea Poplingher

Erik Hallnor

Binta M Patel

Terry M Fletcher

Marc D Torrant

Rahul Agrawal

Quang T Le

Anil K Sabbavarapu

Carl C Scafidi

Kimberly C Weier

Arturo L Arizpe

Vijay S R Degalahal

Karthik Subramanian

Monis Rahman

Jared E Bendt

Abdullah Afzal

Steven Scott Varnum

Mohannad M Noah

Ryan D Wells

Russel J Fenger

Erik G Hallnor

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Current control for a multicore processor

In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Controlling power delivery to a processor via a bypass

An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

All-digital closed loop voltage generator

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Selecting a low power state based on cache flush latency determination

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

Low power retention flip-flop with level-sensitive scan circuitry

In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

Controlling telemetry data communication in a processor

Growing community of inventors

Austin, TX, United States of America

Ashish V Choubal