Freescale Semiconductor,inc.

Honeywell International Inc.

Adobe, Inc.

Ashish Sharma

Amit Gupta

Manmohan Rana

Paul Francis McLaughlin

Manish Sharma

James B Eifert

Bikas Maiti

Chetan Verma

Norman Raymond Swanson

Jehoda Refaeli

Thomas W Liston

Sanjeev Kumar Jain

Rajesh Ramesh

Piyush Kumar Mishra

Sunil S Bale

Srinivasan Rajagopal

Anubhav Jain

Benoy Joseph

Jay M Doyle

Techniques are disclosed for assigning a geographical location to a photograph of a landscape. A geographic location tag is calculated from raw sensor data and a three-dimensional terrain map that corresponds to the landscape in the photograph. One technique includes calculating a two-dimensional ideal view projection of a camera used to take the landscape photograph based at least in part on a geographic location of the camera when the landscape photograph was taken and a field of view of the camera when the landscape photograph was taken. At least one of the topographical features visible from the camera based on the two-dimensional ideal view projection is selected from a three-dimensional terrain map representing a plurality of topographical features within a geographic region. At least one geographic location tag representing at least one of the selected topographical features is assigned to the landscape photograph.

Geotagging a landscape photograph

A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.

Memory device redundancy management system

A memory device that accurately tracks memory operations includes a vertical loopback for tracking a sense clock signal to a row address decoder, and read and write reference bit lines in a reference column that include loopbacks for vertically tracking a selected bit line during read and write operations. Preferably the widths of word lines and a sense line are equal to enable the sense line to horizontally track any selected word line. The memory device also includes tri-state input/output (I/O) latches to latch sense amplifier outputs. A drive circuit of the tri-state I/O latch is disabled when the output is available at the corresponding sense amplifier and enabled when the output is latched by the latch circuit.

Memory device

A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.

System and method for soft error detection in memory devices

A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects a word line. The column address decoder enables a bit line. The data is sensed from a bit cell corresponding to the selected word line and the enabled bit line by a corresponding sense amplifier and delivered on a data output pin of the ROM. The control signals for enabling the bit line and the sense amplifier operate at a higher voltage than supply voltage of the ROM. This reduces the ROM read time.

Read only memory and method of reading same

A method includes receiving a request to install a software release, where the software release is to be installed on a first device and/or a second device. The method also includes initiating installation of the software release on the second device and determining whether or not a user wishes to continue with the installation of the software release. The method further includes initiating installation of the software release on the first device if the user wishes to continue. In addition, the method includes restoring a second software release on the second device if the user does not wish to continue. The first and second devices may represent redundant devices, such as a redundant set of controllers in a process control system or a redundant set of I/O modules that facilitate communication between one or more controllers and one or more process elements in the process control system.

Apparatus and method for allowing a fail-back to a prior software release in a process control system

A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.

Low power read scheme for read only memory (ROM)

A parallel operation keyboard (POK) which enables a user to provide multiple inputs simultaneously in managing a process control plant. A lock is provided to disable such simultaneous inputs. In an embodiment, multiple groups of keys are provided, with each group of keys being operable independently to modify the parameter value of a corresponding control loop. A network management station (NMS) and a server are designed to provide a suitable interface. In one implementation, each group of keys contains four keys respectively specifying increasing the parameter value, decreasing the parameter value, manual mode (in which the present level of the variable is controlled by the increase/decrease keys) and normal mode (in which the set point, i.e., the desired value, for the variable is controlled).

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New Delhi, India

Ashish Sharma