Intel Corporation

Ashish S Gadagkar

Zohar Bogin

David D Lent

Narendra S Khandekar

Tuong P Trieu

Vincent E VonBokern

Robert F Kubick

Manish Muthal

Wishwesh Anil Gandhi

A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

Abort of DRAM read ahead when PCI read multiple has ended

In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.

Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe

An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.

Avoiding livelock when performing a long stream of transactions

An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.

Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge

A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.

Method and apparatus for propagating a signal between synchronous clock

A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.

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Sunnyvale, CA, United States of America

Ashish S Gadagkar