Texas Instruments Corporation

Ashish Ojha

Krishnamurthy Ganapathi Shankar

Priyank Anand

Siddhartha Gopal Krishna

Venkatesh Guduri

Ganapathi Hegde

Venkata Naresh Kotikelapudi

Divyasree J

Chinmay Jain

Anand Gopalan

Ganapathi Shankar Krishnamurthy

Clark Douglas Kinnaird

Nicholas James Oborny

Arun Tej Vemuri

Kalpana Suryawanshi

Richeek Maitra

Sarangan Thirumavalavan

Examples of contactor controllers, systems and methods enable quick-turn-off (QTO) using an output voltage of a contactor controller when its supply voltage is below a threshold but does not interfere with QTO when sufficient supply voltage is available. In an example, when VM loss occurs, a high-side (HS) clamp of a contactor controller is disabled, and a low-side (LS) clamp current is generated using the output voltage. The LS clamp current may be adjusted to achieve a desired QTO voltage. In another example, a HS clamp is disabled and the charging of the gate of a LS field-effect transistor (FET) is enabled only when the output voltage increases above a power-off QTO threshold (less than the LS clamp voltage); the QTO voltage is set by a voltage detection and comparison circuit of the contactor controller.

Quick turn off of contactor system during power off

In an example, a system includes a first transistor and a second transistor, the first transistor and the second transistor configured to provide current to a load. The system also includes a sense transistor coupled to the first transistor, the sense transistor configured to sense a current flowing through the first transistor. The system includes an amplifier coupled to the sense transistor, where the amplifier includes a first input, a second input, and an output. The system also includes pre-bias circuitry coupled to the amplifier, where the pre-bias circuitry is configured to provide a voltage to the first input of the amplifier responsive to the first transistor being off, where the voltage biases the amplifier.

Pre-biased dual current sensing

A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.

Systems and methods for regulation of propagation delay in DC motor drivers

An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.

Systems and methods for regulating slew time of output voltage of DC motor drivers

Disclosed is a ripple counter with a dynamic bandpass filter for a DC motor. The ripple counter includes a current sense amplifier configured to provide an analog voltage responsive to an inline current in rotor windings of the DC motor. The ripple counter also includes an analog-to-digital converter configured to provide a digital signal responsive to the analog voltage. The ripple counter also includes a digital filter configured to receive the digital signal and a clock signal and configured to vary a frequency response to provide a filtered ripple current. The ripple counter also includes a digital comparator circuit configured to receive the filtered ripple current and to provide a pulsed output. The ripple counter also includes a clock generator configured to detect the frequency of the pulsed output and to provide the clock signal responsive to the detected frequency.

Ripple counter with dynamic bandpass filter for DC motor

Examples of contactor controllers, systems and methods time-modulate levels of high-side (HS) and low-side (LS) clamp voltages in a contactor controller to switch a path through which current flows during quick-turn-off (QTO) of the contactor controller. One of the clamp voltages is at a high level and the other is at a low level. The output voltage of the contactor controller is held at the low level. The path switching may be a function of one or more parameters. In a configuration, the level of a supply voltage of the contactor controller is monitored and used to control the path switching. In a configuration, temperatures of HS and LS transistors of the contactor controller are monitored and used to control the path switching. Control of the path switching may be performed to dissipate power in a larger area to increase thermal performance of the contactor controller. Both clamps may remain active throughout the QTO process, providing redundancy and safety.

Time multiplexing voltage clamping in coil driving circuit for a contactor during quick turn off

A driver circuit includes a first switch which has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a high-side gate, and a third terminal coupled to receive a voltage supply enable signal. The first switch is operable to connect the voltage supply terminal to the high-side gate responsive to the voltage supply enable signal. The driver circuit includes a second switch which has a first terminal coupled to a charge pump terminal, a second terminal coupled to the high side gate, and a third terminal coupled to receive a charge pump enable signal. The second switch is operable to connect the charge pump terminal to the high-side gate responsive to the charge pump enable signal.

Driver circuit for full-bridge DC motor driver system

A circuit includes a first transistor, a second transistor, and a sense transistor. The first current terminals of the first and second transistors are coupled together at a power supply node. The control terminals of the second and third transistors are coupled together. The second current terminals of the first, second, and third transistors are coupled together. The sense resistor is coupled between the first current terminals of the first and second transistors and the first current terminal of the third transistor. The first and second transistors are configured such that during a first mode of operation, current to a load flows through the first and second transistors, and during a second mode of operation, current to a load is discontinued through the first transistor yet flows through the second transistor.

Over-current protection circuit

A circuit includes an input terminal, a first transistor, a second transistor, a comparator, a voltage reference circuit, and a control circuit. The first transistor includes a first terminal coupled to the input terminal. The second transistor includes a first terminal coupled to the input terminal. The comparator includes a first terminal coupled to the input terminal. The voltage reference circuit is coupled to a second terminal of the comparator. The control circuit includes an input, a first output, and a second output. The input is coupled to an output of the comparator. The first output is coupled to a second terminal of the first transistor. The second output is coupled to a second terminal of the second transistor.

Open load detection circuits

A control circuit includes a first high-side transistor coupled between a voltage supply terminal and the first terminal of a DC motor and a second high-side transistor coupled between the voltage supply terminal and the second terminal of the DC motor. The control circuit includes a first low-side transistor coupled between a ground terminal and the first terminal of the DC motor and a second low-side transistor coupled between the ground terminal and the second terminal of the DC motor. The control circuit includes a first pull-up resistor coupled between the voltage supply terminal and a gate terminal of the first low-side transistor and a second pull-up resistor coupled between the voltage supply terminal and a gate terminal of the second low-side transistor. The pull-up resistors apply bias currents to turn ON the first and second low-side transistors to provide a conductive path to brake the DC motor.

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Ashish Ojha