Freescale Semiconductor,inc.

Nxp Usa, Inc.

Centillium Communications, Inc.

Ashish Mathur

Sandeep Jain

Sourav Roy

Vijay Bhargava

Diviya Jain

Srinivasan Gopalaswamy

Pradeep Jain

A self-optimizing System-on-Chip (SOC) includes multiple cores, multiple hardware accelerators, multiple memories and an interconnect framework. The SOC also includes a machine learning (ML) module that uses data flow information to build a ML network dynamically and configures all the various hardware blocks autonomously, to achieve predetermined application performance targets. The SOC is able to recover from hangs caused when testing various configuration settings. The SOC also avoids configuration settings that cause severe drops in performance.

Self-optimizing multi-core integrated circuit

Systems and method for idle loop detection and control are disclosed. A processor operates in operating modes including an active mode and a disabled mode, and an interconnect bus is coupled between the processor and one or more additional electronic circuits. Logic within the processor is coupled to snoop the interconnect bus, and the logic is programmed to detect a new idle loop based upon repeated instructions on the interconnect bus and to place the processor in the disabled mode based upon execution of the new idle loop, which represents a previously unknown idle loop for the processor. Further, the logic can be programmed to store state data for the processor when the new idle loop is detected, and the logic can also be programmed to place the processor in the active mode based upon detection of a wakeup event for the new idle loop on the interconnect bus.

Idle loop detection and control for processors

A system and method to record and trace data exchanges between cooperating hardware unit operations and software unit operations, providing an efficient mechanism to trace back to a root cause point from an observed failure point in a series of executed instructions performed within a data processing system. A data debug memory records information pertaining to each system memory access performed by instructions executed by the hardware and software units into separate memory information blocks. Linked relationships are created between certain ones of the memory information blocks to represent data dependencies that occurred between the instructions. These linked relationships may then be utilized to generate lists that map the various data dependencies between the executed instructions.

Hardware and software debug using data dependency tracing

A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

Multi-threaded system for performing atomic binary translations

A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.

Method and system for estimating power consumption of integrated circuit design

A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

Method for estimating processor energy usage

Precision of multi-stage digital signal processing is increased by preserving least significant bits of one or more output samples of a particular processing stage, having finite word widths, while avoiding the loss of most significant bits. The technique is applicable to one or more stages of multi-stage digital signal processing, thereby increasing precision therein and the signal-to-noise ratio. A plurality of output samples are calculated using a plurality of input samples, and the dynamic range of one or more of the output samples is decreased if the output sample can be represented in a smaller dynamic range without losing a significant bit. The input samples of a particular stage, obtained from the output samples of a previous stage, may further be normalized so that the input samples are represented in the same dynamic range before being processed.

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New Delhi, India

Ashish Mathur