Texas Instruments Corporation

Ashish Manjrekar

Bryan E Bloodworth

Echere Iroaga

Indumini W Ranmuthu

Paul Merle Emerson

Patrick Michael Teterud

Taras Vasylyovych Dudar

James Nodar

Rajkumar Jayaraman

Nilakantan Seshan

Benjamin Sarpong

Seungwoo Jung

Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers

Methods and apparatus for proximity detection of hard disk drive read heads are disclosed. A disclosed method comprises forming a first signal having a frequency, a first amplitude, and a first offset voltage, forming a second offset voltage substantially equal to the first offset voltage from the first signal, amplifying the amplitude of the first signal to cause the resonant signal to have a second amplitude greater than the first, and forming a second signal having a frequency indicative of the location of a read head relative to a platter of a hard disk drive.

Methods and apparatus for proximity detection of hard disk drive read heads

An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information; the apparatus includes: (a) a read signal control unit receiving the input signal at a control unit input locus; the control unit is coupled with the output locus and controls the read signal; (b) a plurality of switches; and (c) a plurality of bias arrays coupled with the switches. A first bias array set cooperates with the plurality of switches in a first orientation to couple the first bias array set with the control unit to establish a first operational mode. A second bias array set cooperates with the plurality of switches in a second orientation to couple the second bias array set with the control unit to establish a second operational mode.

Apparatus and method for providing a read signal for an information processing device

The present invention relates to a method of enhancing a preamplifier read recovery in a hard disk drive system and comprises the steps of determining whether the hard disk drive system is transitioning from a non-read state to a read state and initiating a non-read state to a read state transition sequence when a transition from the non-read state to the read state is determined. The transition sequence is independent of a type of non-read state prior to the transitioning. After the non-read state to read state transition sequence is complete the read mode is initiated. In addition, the invention comprises a system for controlling a transition from a non-read state to a read state associated with a preamplifier in a hard disk drive system. The system comprises a detection circuit operable to detect a completion of the non-read state and a non-read state to read state circuit operable to execute a series of events to transition from the non-read state to the read state, wherein the series of events is the same regardless of a type of non-read state. Further, the system comprises a read state initiation circuit operable to initiate the read state after the execution of the series of events.

Preamplifier read recovery parade

A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.

Relative timing sequence for reader amplifiers

A circuit ( ) and method ( ) for protecting read heads ( ) of a hard-disk drive system ( ). Capacitor C is controllably coupled to a dummy head R during a V mode, so that capacitor C has a low, predictable voltage upon returning to I mode, protecting the read heads ( ) from damage. The circuit ( ) includes logic ( ) and algorithm ( ) determining when to couple the capacitor C to the dummy head R during a servo bank write (SBW) sequence.

Read head protection circuit and method

A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit operatively coupled to the bias voltage circuit stage which is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. A head select boost recovery circuit is also operatively coupled to the bias voltage circuit and is configured to increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the circuits allow for a concurrent head switch and current bias switch and avoids the problems associated with the prior art.

Capacitor bias recovery methodology

An offset circuit to correct an offset between differential signals includes a read circuit to read the differential signals, a circuit to measure the offset of the differential signals, and a programmable trim circuit to compensate for the offset of said differential signals.

Write to read switching time trim circuit

The present invention provides an apparatus, system and method of improving the bias response time for pre-amplifier circuits which utilize noise reduction capacitors . The system uses a quick recovery circuit electrically connected to the capacitive node of the pre-amplifier circuit. The quick recovery circuit comprises a gain amplifier with a resistive input and a controlled current source . The controlled current source corresponds to adjustments in a controlled current source of the pre-amplifier and is electrically connected to the resistive input of the gain amplifier . The gain amplifier can be selectively switched to operatively connect an output to the capacitive node of the pre-amplifier circuit.

Growing community of inventors

Dallas, TX, United States of America

Ashish Manjrekar