Texas Instruments Corporation

Other

Qualcomm Incorporated

Ashish Lachhwani

Gireesh Rajendran

Rakesh Kumar

Alok Prakash Joshi

Subhashish Mukherjee

Debapriya Sahu

Nir Tal

Apu Sivadas

Anand Kannan

Rittu Kulwant Sachdev

Vikas Singh

Amrith Sukumaran

David Cohen

According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.

PLL system and device with a low noise charge pump

According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.

Digital to analog converter tolerant to element mismatch

Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.

Digital controlled oscillator and switchable varactor for high frequency low noise operation

Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency.

Front-end architecture for transmitter

A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

Low power excess loop delay compensation technique for delta-sigma modulators

An active filter circuit includes an inductance-capacitance (LC) circuit () for wireless frequency input, a bi-directional mixer () and a filter impedance () series-coupled across at least part of the LC circuit (), and another mixer () coupled to at least some portion of the LC circuit. Other circuits, processes, receivers, transmitters and transceivers are disclosed.

Narrow band RF filter circuits, devices and processes using impedance translation

A method, system, and apparatus of a DC current based on chip RF power detection scheme for a power amplifier are disclosed. In one embodiment, a method includes generating a scaled current from an other current associated with power amplifier, transforming the scaled current (e.g., the scaled current may be scaled to the other current value) into a digital signal and using the digital signal to set a radio frequency power value of an antenna of the antenna module. The method may include transforming the scaled current into a voltage signal. The method may also include transforming the voltage signal into the digital signal. The method may also include generating a current mirror from a low dropout regulator.

DC current based on chip RF power detection scheme for a power amplifier

A low-power receiver front-end includes a transconductance amplifier that produces a single-ended current signal in response to a single-ended voltage signal. An output of the transconductance amplifier is provided to an LC tuned circuit. At resonance, the LC tuned circuit generates a differential current signal in response to the single-ended current signal. Single-ended current signals corresponding to the resonant frequency of the LC tuned circuit are converted into differential signals. Further, the LC tuned circuit amplifies the differential current signals by an associated quality factor. Further, a mixer is coupled to an output of the LC tuned circuit. The mixer generates IF signals in response to the differential current signals.

Receiver front end

Low noise amplifier circuit. The low noise amplifier circuit includes an amplifier that amplifies an input to provide an output. The amplifier is coupled to an input terminal. The circuit also includes a device in a cascode connection with the amplifier. The circuit further includes a tuning circuit coupled to the device to phase shift the output. Further, the circuit includes a feedback circuit that is responsive to a phase-shifted output to enhance gain of the amplifier. The feedback circuit is coupled to the tuning circuit and the amplifier.

Low noise amplifier circuit

Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Oscillator circuit for radio frequency transceivers

A local oscillator (LO) generator architecture using a wide tuning range oscillator is disclosed. In one embodiment, a wide tuning oscillator based LO generator system includes a wide tuning range oscillator for generating a signal with a first initial frequency or a second initial frequency in response to a control voltage, a first frequency controlling circuit for converting the first initial frequency of the signal into a final frequency, and a second frequency controlling circuit for converting the second initial frequency of the signal into the final frequency.

Growing community of inventors

Bengaluru, India

Ashish Lachhwani