Nvidia Corporation

Intel Corporation

Ashish Karandikar

Shirish C Gadre

Stephen Donald Lew

Franciscus W Sijstermans

Christopher Thomas Cheng

Zhiqiang Jonathan Su

Jonah Matthew Alben

Shane J Keil

Anujan Varma

Frederick R Gruner

Gunaseelan Ponnuvel

Mark Heuchert

Pooja Agarwal

Kaustubh Sanghani

Amir H Salek

In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.

Enhanced in-system test coverage based on detecting component degradation

A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.

Pipelined L2 cache for memory transfers for a video processor

A method for implementing command acceleration. The method includes receiving a first set of instructions from a first processor, wherein the first set of instructions are formatted in accordance with a microarchitecture of the first processor. The first set of instructions are translated into a second set of instructions, wherein the second set of instructions are formatted in accordance with a microarchitecture of a second processor. The second set instructions are then transmitted to the second processor for execution by the second processor.

Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions

A method for using a programmable DMA engine to implement memory transfers and video processing for a video processor. A DMA control program is configured for controlling DMA memory transfers between a frame buffer memory and a video processor. The DMA control program is stored in the DMA engine. A DMA request can be received from the video processor. The DMA control program is executable to implement the DMA request for the video processor. The DMA engine is operable to execute low-level command for accessing the frame buffer memory to implement a high-level command.

Programmable DMA engine for implementing memory transfers and video processing for a video processor

A configurable SIMD engine in a video processor for executing video processing operations. The engine includes a SIMD component having a plurality of inputs for receiving input data and a plurality of outputs for providing output data. A plurality of execution units are included in the SIMD component. Each of the execution units comprise a first and a second data path, and are configured for selectively implementing arithmetic operations on a set of low precision or high precision inputs. Each of the execution units have a first configuration and a second configuration, such that the first data path and the second data path are combined to produce a single high precision output in the first configuration, and such that the first data path and the second data path are partitioned to produce a respective first low precision output and second low precision output in the second configuration.

Configurable SIMD engine with high, low and mixed precision modes

A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Video processor having scalar and vector components

A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.

Latency tolerant system for executing video processing operations

A method for implementing multi context execution on a video processor having a scalar execution unit and a vector execution unit. The method includes allocating a first task to a vector execution unit and allocating a second task to the vector execution unit. The first task is from a first context in the second task is from a second context. The method further includes interleaving a plurality of work packages comprising the first task and the second task to generate a combined work package stream. The combined work package stream is subsequently executed on the vector execution unit.

Multi context execution on a video processor

A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Multidimensional datapath processing in a video processor

A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.

State machine control for a pipelined L2 cache to implement memory transfers for a video processor

The memory splitter chip couples multiple DRAM units to the PPU, thereby expanding the memory capacity available to the PPU for storing data and increasing the overall performance of the graphics processing system. The memory splitter chip includes logic for managing the transmission of data between the PPU and the DRAM units when the transmission frequencies and the burst lengths of the PPU interface and the DRAM interfaces differ. Specifically, the memory splitter chip implements an overlapping transmission mode, a pairing transmission mode or a combination of the two modes when the transmission frequencies or the burst lengths differ.

Increasing memory capacity of a frame buffer via a memory splitter chip

A method for context switching on a video processor having a scalar execution unit and a vector execution unit. The method includes executing a first task and a second task on a vector execution unit. The first task in the second task can be from different respective contexts. The first task and the second task are each allocated to the vector execution unit from a scalar execution unit. The first task and the second task each comprise a plurality of work packages. In response to a switch notification, a work package boundary of the first task is designated. A context switch from the first task to the second task is then executed on the work package boundary.

Context switching on a video processor having a scalar execution unit and a vector execution unit

A stream based memory access system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A frame buffer memory is included for storing data for the scalar execution unit and the vector execution unit. A memory interface is included for establishing communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory comprises a plurality of tiles. The memory interface implements a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit.

Stream processing in a video processor

In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the certain address from the memory device. The processing device dynamically detects boundaries for the data block read by detecting an alignment pattern in data received from the memory device. Other embodiments are otherwise disclosed herein.

Growing community of inventors

Sunnyvale, CA, United States of America

Ashish Karandikar