Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Ashish Ghai

Daniel Joseph Linnen

Srikar Peesari

Avinash Rajagiri

Dongxiang Liao

Dana Lee

Kirubakaran Periyannan

Jagdish Sabde

Shantanu Gupta

Ekamdeep Singh

Kalpana Vakati

Yuvaraj Krishnamoorthy

Deepak Bharadwaj

Jianmin Huang

Chang Hua Siau

Rohit Sehgal

Mark Shlick

Shrikar Bhagath

Mrinal Kochar

Philip David Reusswig

Gopinath Balakrishnan

Lakshmi Kalpana Vakati

Cheng-Chung Chu

Sukhminder Singh Lobana

Kapil Verma

Khanfer Kukkady

Bin Wu

Ekam Singh

Maythin Uthayopas

Janet George

Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Implementation of deep neural networks for testing and quality control in the production of memory devices

A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.

Encryption detection and backup management

A non-volatile storage apparatus receives first data from an entity external to the non-volatile storage apparatus, combines the first data with other data being stored in the non-volatile storage apparatus to create combined data, performs a programming process to program the first data into a first location, determines that the programming process failed, intentionally corrupts the first data programmed into the first location, recovers the first data from the combined data, and reprograms the recovered first into a second location.

Non-volatile storage system with program failure recovery

A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

NAND field use erase plus defect detections

A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Location-based authentication and monitoring for data storage devices

A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Partial memory die with inter-plane re-mapping

Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Multi-plane memory management

A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Partial memory die

Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.

Determination of fast to program word lines in non-volatile memory

Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.

Leakage current detection in 3D memory

To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.

Non-volatile memory with in field failure prediction using leakage detection

A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of 'goodness' or a level of 'badness' for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.

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San Jose, CA, United States of America

Ashish Ghai