Intermolecular, Inc.

Applied Materials, Inc.

Globalfoundries Inc.

The Dow Chemical Company

Ashish Bodke

Kevin Kashefi

Olov B Karlsson

Mark Harold Clark

Zhendong Hong

Paul Raymond Besser

Prashant B Phatak

Usha Raghuram

Keyvan Kashefizadeh

Divya Pisharoty

Mei Yin Chang

Hoon Sik Kim

Dipankar Pramanik

Kisik Choi

Jinping Liu

Xinyu Fu

Amol Ramesh Joshi

Zhigang Xie

Wonwoo Kim

Jingang Su

Winsor Lam

Salil Mujumdar

Yiochiro Tanaka

Susie Tzeng

Xunyuan Zhang

Frank Greer

Sean Barstow

Lanny D Schmidt

Vivian Ryan

Ratsamee Limdulpaiboon

Bongki Lee

Edwin Adhiprakasha

Nobi Fuchigami

Karthik Ramani

J Watanabe

Abhijit Pethe

Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525&#xb0; C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.

Low temperature deposition of low loss dielectric layers in superconducting circuits

Methods for processing substrates are provided herein. In some embodiments, a method of processing a substrate within a process chamber having an electrostatic chuck to support a substrate in a processing region of the process chamber and a target disposed opposite the electrostatic chuck, wherein the target comprises a target material to be deposited on the substrate, may include disposing a substrate on the electrostatic chuck; providing a process gas to the processing region; igniting a plasma in the processing region from the process gas while the substrate is disposed on the electrostatic chuck with no chucking voltage provided to clamp the substrate to the electrostatic chuck; and depositing target material on the substrate to form a first barrier layer while no chucking voltage is provided, wherein the target material is sputtered from the target via the plasma.

Methods of preventing plasma induced damage during substrate processing

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.

Diamond like carbon (DLC) as a thermal sink in a selector stack for non-volatile memory application

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Gate structures for transistor devices for CMOS applications and products

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Photo-induced MSM stack

Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu&#x2014;Mn seed layer between the Ta&#x2014;Ti and copper.

Combinatorial screening of metallic diffusion barriers

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.

Tunneling barrier creation in MSM stack as a selector device for non-volatile memory application

Transistors having a work function layer and methods of fabricating thereof are disclosed herein. The work function layer includes aluminum and titanium layers which are deposited in separate atomic layer deposition (ALD) operations. The depositions of the titanium layers and the aluminum layers may be separated by a purge operation or even performed in different ALD chambers. The work function layer may include alternating sets of titanium layers and sets of aluminum layers, thereby forming a nanolaminate structure. As such, a ratio of titanium to aluminum may be controlled and varied as needed throughout the thickness of the work function layer. For example, the work function layer may be titanium rich at the surface facing the gate dielectric in order to reduce or prevent diffusion of aluminum into the gate dielectric.

Deposition of titanium-aluminum layers

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Methods for fabricating integrated circuits including fluorine incorporation

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Methods of forming gate structures for transistor devices for CMOS applications

Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.

Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach

Oxides (e.g., native or thermal silicon oxide) are etched from underlying silicon with a mixture of fluorine and oxygen radicals generated by a remote plasma. The oxygen radicals rapidly oxidize any uncovered bare silicon areas, preventing the pitting that can result from fluorine etching bare silicon more rapidly than it etches the surrounding oxide. A very thin (few &#x212b;), highly uniform passivation layer remaining on the silicon after the process may be left in place or removed. An oxygen-impermeable layer may be formed in-situ immediately afterward to prevent further oxidation. A pre-treatment with oxygen radicals alone fills pores and gaps in the oxide before etching begins.

Oxide removal by remote plasma treatment with fluorine and oxygen radicals

Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.

Methods of forming a layer for barrier applications in an interconnect structure

Methods for forming titanium nitride layers are provided herein. In some embodiments, a method of forming a titanium nitride layer on a substrate may include providing a substrate into a processing chamber having a target comprising titanium disposed therein; supplying a nitrogen-containing gas into the processing chamber; sputtering a titanium source material from the target in the presence of a plasma formed from the nitrogen-containing gas to deposit a titanium nitride layer on the substrate; and upon depositing the titanium nitride layer to a desired thickness, forming a magnetic field that biases ions in the processing chamber away from the substrate.

Methods for forming a titanium nitride layer

Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical valor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.

Growing community of inventors

San Jose, CA, United States of America

Ashish Bodke