Arm Limited

Ashish Bhardwaj

Bo Zheng

Fakhruddin Ali Bohra

Lalit Gupta

El Mehdi Boujamaa

Cyrille Nicolas Dray

Nicolaas Klarinus Johannes Van Winkelhoff

Durgesh Kumar Dubey

Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

Circuit architecture to derive higher mux from lower mux design

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Noida, India

Ashish Bhardwaj