Atrenta, Inc.

Ashish Bansal

Mohammad Homayoun Movahed-Ezazi

Paras Mal Jain

Maher Mneimneh

Namit Gupta

Shaker Sarwary

A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.

System and method for metastability verification of circuits of an integrated circuit

A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.

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New Delhi, India

Ashish Bansal