Freescale Semiconductor,inc.

Transwitch Corporation

Ashis Maitra

Chetan Verma

Gaurav Goyal

Kulbhushan Misri

Amit Roy

Vijay Tayal

Amit Kumar Dey

Pushkal Yadav

Kumar Shakti Singh

Sachin Mathur

Ateet Mishra

Harkaran Singh

Yudhishthira Kundu

Diljit Singh

Chitra Wadhwa

Amandeep Singh Gujral

Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.

Flip-flop cell with configurable delay

A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.

System for partitioning integrated circuit design based on timing slack

Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

Time multiplexed SONET line processing

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New Delhi, India

Ashis Maitra