Apple Inc.

Semiconductor Components Industries, LLC

Aptina Imaging Corporation

Ashirwad Bahukhandi

Chiajen Lee

Taehee Cho

Gennadiy A Agranov

Mansour Keramat

Xiangli Li

Claus Molgaard

Hai Yan

Hyunsik Park

Isao Takayanagi

Nikolai E Bock

Qi Wang

Ali Mesgarani

Dongsoo Kim

Dusan Stepanovic

Daniel R Hennigan

Kai Min

Nick Chang

Brian Liebowitz

Timothy J Bales

Ju-Hyung Kim

A camera may include a substrate for placing components. An image sensor having a light-receiving side and an opposite non-light-receiving side may be attached to a first side of the substrate to receive light from one or more lenses of the camera to capture an image. The camera may also include one or more additional components separate and distinct from the image sensor. The additional components may be placed beneath the non-light-receiving side of the image sensor. The components may be attached to a second side of the substrate opposite the first side where the image sensor is mounted at least partially inside one or more recesses, or embedded at least partially inside the substrate.

Substrate to place components for camera size reduction

A method of reading a pixel value from an image sensor housed with a set of components includes determining a current state of the set of components; adjusting, at least partly responsive to the current state of the set of components, a correlated double sampling (CDS) time; and performing, in accordance with the adjusted CDS time, a CDS readout of at least one pixel in a pixel array of the image sensor.

Dynamic correlated double sampling for noise rejection in image sensors

An image sensing system is disclosed. The image sensing system includes an array of pixel circuits and a multiplexer configured to convey an output signal from a selected one of the pixel circuits. The output signal from the selected one of the plurality of pixel circuits is converted from analog to digital by a successive approximation register (SAR) analog-to-digital converter (ADC). A control circuit is provided to cause the SAR ADC power cycling with shaped power control signal. The SAR ADC comparator pre-amp with integrate-reset causes reduced power to the theoretical limit for imaging systems. The control circuit causes quantization process of selected ones of the pixel circuits to be repeated one or more times during the processing.

High speed, low power image sensor system

A pixel circuit and method for operating the same is disclosed. The circuit includes a first driver circuit coupled to receive an analog pixel data, transfer signal and reset signal. The circuit further includes a source follower transistor having a source terminal coupled to a column node, and a gate terminal coupled to the first driver circuit. The circuit further includes a second driver circuit coupled to receive the transfer signal and the reset signal. The second driver circuit is capacitively coupled to the column node through a first capacitor.

Clock feedthrough compensation in image sensor systems

Pixel binning is performed by summing charge from some pixels positioned diagonally in a pixel array. Pixel signals output from pixels positioned diagonally in the pixel array may be combined on the output lines. A signal representing summed charge produces a binned 2&#xd7;1 cluster. A signal representing combined voltage signals produces a binned 2&#xd7;1 cluster. A signal representing summed charge and a signal representing combined pixel signals can be combined digitally to produce a binned 2&#xd7;2 pixel. Orthogonal binning may be performed on other pixels in the pixel array by summing charge on respective common sense regions and then combining the voltage signals that represent the summed charge on respective output lines.

Pixel binning in an image sensor

Pixel binning is performed by summing charge from some pixels positioned diagonally in a pixel array. Pixel signals output from pixels positioned diagonally in the pixel array may be combined on the output lines. A signal representing summed charge produces a binned 2&#xd7;1 cluster. A signal representing combined voltage signals produces a binned 2&#xd7;1 cluster. A signal representing summed charge and a signal representing combined pixel signals can be combined digitally to produce a binned 2&#xd7;2 pixel. Orthogonal binning may be performed on other pixels in the pixel array by summing charge on respective common sense regions and then then combining the voltage signals that represent the summed charge on respective output lines.

Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.

Ramp and successive approximation register analog to digital conversion methods, systems and apparatus

An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal.

Offset injection in an analog-to-digital converter

Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry. The column readout circuitry on each column line may include signal processing circuitry and a latch circuit. The latch circuit on each column line may be used to selectively enable and disable the signal processing circuitry on that column line. Each latch circuit may be coupled to first and second signal lines for globally enabling and disabling the signal processing circuitry on all of the column lines. Each latch circuit may be coupled to column decoder circuitry. The column decoder circuitry may provide a column-select signal to latch circuits on a chosen subset of column lines that enables the signal processing circuitry on those column lines by setting those latch circuits.

Imaging systems with selectable column power control

Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array.

Column parallel readout image sensors with shared column analog-to-digital converter circuitry

Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.

Growing community of inventors

San Jose, CA, United States of America

Ashirwad Bahukhandi