International Business Machines Corporation

Ashim Dutta

Chih-Chao Yang

Ekmini Anuja De Silva

John Christopher Arnold

Dominik Metzler

Michael Rizzolo

Theodorus E Standaert

Saumya Sharma

Nelson M Felix

Tianji Zhou

Daniel C Edelstein

Jennifer Church

Luciana Meli Thompson

Praveen Joseph

Baozhen Li

Oscar Van Der Straten

Yann Mignot

Chi-Chun Liu

Timothy Mathew Philip

Sagarika Mukesh

Lili Cheng

Ruilong Xie

Lawrence Alfred Clevenger

Son Van Nguyen

Jon Michael Slaughter

Indira P Seshadri

Dexin Kong

Jing Guo

Saba Zare

Isabel Cristina Chu

Daniel Schmidt

Takeshi Nogami

Benjamin David Briggs

Wenyu Xu

Christopher J Penny

Koichi Motoyama

Kisik Choi

Terry Allen Spooner

Donald Francis Canaperi

Cornelius Brown Peethala

Christopher Joseph Waskiewicz

Yongan Xu

Shyng-Tsong Chen

Huimei Zhou

Tao Li

Tsung-Sheng Kang

Iqbal Rashid Saraf

Eric Raymond Evarts

Matthew T Shoudy

Karthik Yogendra

Abraham Arceo De La Pena

Vinh Hoang Luong

Devika Sil

Lijuan Zou

Kedari Matam

Shravana Kumar Katakam

Ruturaj Nandkumar Pujari

Luciana M Thompson

An MRAM device is provided. The MRAM device includes a first dielectric cap layer formed on an underlying layer, a second dielectric cap layer formed on the first dielectric cap layer, the first dielectric cap layer including a lower-κ material than that of the second dielectric cap layer. The MRAM device also includes a bottom electrode contact (BEC) formed through the first dielectric cap layer and the second dielectric cap layer, an MRAM stack formed on the BEC, and wherein the second dielectric cap layer surrounds an upper portion of the BEC.

Layered bottom electrode dielectric for embedded MRAM

A first BEOL layer, including a first and a second signal line, a conformal dielectric surrounding an upper portion of a vertical sidewall of each of the first signal line and the second signal line, an air gap between the first and the second signal line, a vertical side boundary of the air gap is a vertical side surface of the first signal line. Forming a first and a second metal line in a sacrificial material in a first BEOL layer, removing the sacrificial material, forming a conformal dielectric surrounding vertical side surfaces of the first and the second metal line, an air gap between the first and the second metal line exposes an upper horizontal surface of a dielectric layer below the first BEOL layer, growing a dielectric selectively from an upper portion of the conformal dielectric, the air gap remains between the first and the second metal line.

Air gap in beol interconnect

Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

Back-end-of-line thin film resistor

An MRAM device is provided. The MRAM device includes a semiconductor device comprising a bottom contact electrode (BEC), and an MRAM stack formed on the BEC. A width of an upper portion of the BEC is less than a width of the MRAM stack.

MRAM bottom electrode contact with taper profile

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer

A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Fabrication of embedded memory devices utilizing a self assembled monolayer

A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.

Advanced metal interconnect

A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.

Probe pad with built-in interconnect structure

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in the substrate. A metal line on a metal interconnect of the non-memory area interconnect structure is formed. A first dielectric layer on exposed surfaces of the non-memory area is formed. A hardmask is formed on the dielectric layer. A second dielectric layer is formed on exposed surfaces of the memory area. A bottom metal contact is formed in a trench, a bottom surface of the bottom metal contact on a top surface of a first metal interconnect of the memory area interconnect structure. A memory element stack pillar is formed on the bottom metal contact.

Tall bottom electrode structure in embedded magnetoresistive random-access memory

A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.

Modified top electrode contact for MRAM embedding in advanced logic nodes

A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Embedded metal contamination removal from BEOL wafers

Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Selective patterning of vias with hardmasks

A semiconductor device includes a dual layer top contact upon a MTJ stack. The dual layer top contact includes lower contact and upper contact. The lower contact may be wider and/or shallower relative to the upper contact. This wide and/or shallow geometry of the lower contact may decrease the propensity for over etching, during the formation of the upper contact, opening downward into the MTJ stack and may therefore prevent undesired shorting of the MTJ stack. Further, the lower contact may further protect the MTJ stack even when the upper contact is misaligned to the MTJ stack.

Dual layer top contact for magnetic tunnel junction stack

A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.

MRAM device with wrap-around top electrode

A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

Additive interconnect formation

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Menands, NY, United States of America

Ashim Dutta