Nvidia Corporation

Other

Ashfaq Shaikh

Ting-Sheng Ku

Chang Hee Hong

Barry A Wagner

Russell R Newcomb

William B Simms

Ting Ku

Amit D Sanghani

Rajesh Anantharaman

Huabo Chen

Shifeng Yu

Punit Kishore

Wen-Hung Lo

Krishna Rajan

One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.

Virtual access of input/output (I/O) for test via an on-chip star network

An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment. As such, embodiments enable different and/or additional calibration operations and/or tests to be performed when compared with conventional loopback configurations.

Loopback configuration for bi-directional interfaces

A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals.

Method and system for a free running strobe tolerant interface

A data sampling apparatus and associated method are provided, including a first inverter receiving a data signal, and inverting the data signal to produce a trigger signal, a first flip-flop receiving the trigger signal, and outputting an output signal, a second flip-flop and a third-flop flop each receiving the output signal from the first flip-flop, the second flip-flop further receiving a strobe signal, and a second inverter inverting the strobe signal, and outputting the inverted strobe signal to the third flip-flop. An output of the second flip-flop indicates a value of the output signal output from the first flip-flop when the strobe signal is of a first state and an output of the third flip-flop indicates a value of the output signal output from the first flip-flop when the strobe signal is of a second state.

Apparatus and method for sampling a data signal in a manner independent of a hold time of the data signal

Embodiments for positioning rising and/or filling edges of data strobe signals are disclosed. One example embodiment may comprise receiving a data signal, positioning an edge of a first delayed data strobe signal associated with the data signal by a first programmable amount, and positioning an edge of a second delayed data strobe signal associated with the data signal by a second programmable amount, wherein the second delayed data strobe signal is shifted approximately one bit-time in relation to the first delayed data strobe signal.

Calibration of separate delay effects for multiple data strobe signals

Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.

Circuit technique to prevent device overstress

Embodiments for providing a plurality of bias voltages to input/output circuitry are disclosed.

Input/output buffer for wide supply voltage range

Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training patterns are received. The presence of errors in the received data pattern is tracked, and from the presence or absence of errors a preferred delay is selected and used for receiving data.

Data sampling clock edge placement training for high speed GPU-memory interface

Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.

Circuit technique to achieve power up tristate on a memory bus

Embodiments of methods, apparatuses, systems and/or devices associated with a bus termination scheme are disclosed.

Bus termination scheme having concurrently powered-on transistors

Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.

Data mask as write-training feedback flag

Embodiments for controlling pre-emphasis driver circuits for electrical signal interconnects within a computer system are disclosed.

Growing community of inventors

San Jose, CA, United States of America

Ashfaq Shaikh