Texas Instruments Corporation

Accenture Global Solutions Limited

Ashesh Parikh

Andrew Marshall

Chi-Chien Ho

Thomas John Smelko

Henry Litzmann Edwards

Anand Seshadri

Rajni J Aggarwal

Jeffrey R Debord

Bradley David Sucher

Toan Tran

Suresh Aswathnarayana

Afzal Husain

Thomas J Aton

William R McKee

Jarvis Benjamin Jacobs

Joshua Intriligator

Alon Arad

Ragnar-Miguel Myhrer

Sharad Sachdev

Tejas Rao

Scott Andrew Alfieri

Mercedes Monroy

Paolo Astro

Willie J Yarbrough

A device may receive demand data associated with a product or a service, multiple forecasting models, and multiple cost functions, and may identify primary parameters for the multiple models based on the demand data. The device may utilize a model to rank the multiple forecasting models and the multiple cost functions based on the primary parameters, and may select optimum primary parameters based on ranking the multiple forecasting models and the multiple cost functions. The device may identify secondary parameters for the multiple forecasting models based on the demand data and the optimum primary parameters. The device may select optimum secondary parameters based on ranking the multiple forecasting models and the multiple cost functions, and may select a forecasting model, from the multiple forecasting models, based on the optimum primary parameters and the optimum secondary parameters. The device may perform one or more actions based on selecting the forecasting model.

Selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting model

A system may receive a cluster prediction requirement. The system may determine a first node conglomerate by sorting a first dataset into a first plurality of nodes. The system may determine a plurality of attributes by sorting a second dataset associated with the cluster prediction requirement. The system may determine a second node conglomerate for each of the plurality of attributes. A node confidence score may be assigned to each of the second plurality of nodes. The system may determine a node graph based on a comparison between the first node conglomerate and the second node conglomerate. The node graph may be iteratively modified based on a node optimization threshold value to generate a harmonized node graph. The node optimization threshold value may be based on a map confidence score allotted to the node graph.

Network optimization

A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Method to improve transistor matching

In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

CMOS-based thermopile with reduced thermal conductance

An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).

Extraction of imaging parameters for computational lithography using a data weighting algorithm

A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.

Computational lithography with feature upsizing

A symmetrical circuit is disclosed (FIG.). The circuit includes a first transistor () having a first channel in a substantial shape of a parallelogram (FIG.A) with acute angles. The first transistor has a first current path () oriented in a first crystal direction (). A first control gate () overlies the first channel. A second transistor () is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path () oriented parallel to the first current path. A second control gate () overlies the second channel.

Transistor layout for manufacturing process control

A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed.

OPC models generated from 2D high frequency test patterns

A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

Carbon nanotube transistors on a silicon or SOI substrate

A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an upper silicon layer mesa island, carbonizing the silicon layer into SiC utilizing a gaseous source, converting the SiC into graphene, forming source/drain regions on opposite longitudinal ends of the graphene, forming gate oxide between the source/drain regions on the graphene, forming gate material over the gate oxide, creating a transistor edge, depositing dielectric onto the transistor edge and performing back end processing.

Method for fabricating graphene transistors on a silicon or SOI substrate

Method for fabricating carbon nanotube transistors on a silicon or SOI substrate

A method () for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask () having a plurality of symmetric and asymmetric test structures thereon, and image processing one or more semiconductor wafers () using the fabricated mask to create a plurality of symmetric and asymmetric resist structures overlying the one or more wafers. At least one critical dimension of the symmetric resist structures and the asymmetric resist structures are measured (), thereby generating symmetric and asymmetric critical dimension data, and a difference between a desired feature size of the symmetric and asymmetric structures and the measured feature size of the symmetric and asymmetric structures is evaluated () in order to generate an optical proximity correction model () based thereon.

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Frisco, TX, United States of America

Ashesh Parikh