Lsi Logic Corporation

Hewlett-packard Development Company, L.p.

Verisilicon Holdings Company Ltd.

Asheesh Kashyap

Tracy Nguyen

Darel N Emmot

Charles H Stewart

Vijayanand Angarai

Michelle Y Che

A prefetch buffer and prefetch method. In one embodiment, the prefetch buffer has a main buffer embodied as a direct-mapped cache, and the prefetch buffer includes: (1) an alias buffer associated with the main buffer and (2) a prefetch controller associated with the main buffer and the alias buffer and operable to cause the alias buffer to store potentially aliasing cachelines of a loop body instead of the main buffer.

Digital signal processor prefetch buffer and method

A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof

A nodal computer network comprises a plurality of nodes grouped into different classes. The classes include at least a first class of fully interconnected nodes and a second class of fully interconnected nodes, and the first class includes a source node having an information packet to be communicated to a destination node. The source node is configured to divide the information packet into segments and to disperse the segments among the nodes of the first class. The nodes of the first class are configured to transmit each of said segments directly to the nodes of said second class, wherein the first class is not fully interconnected with the second class.

Nodal computer network

An error correction code method comprises examining a validator of one of a plurality of data in a data stream at a first processing stage and directing the one of the plurality of data through at least one subsequent processing stage to a corrected output if the validator indicates an error. The method also includes directing the one of the plurality of data to the corrected output if the validator does not indicate an error.

Error correction method and system

A system, circuit, and method are presented for adjusting a prefetch rate of a prefetch unit from a first rate to a second rate by determining a probability factor associated with a branch instruction. The circuit and method may determine the probability factor based on a type of disparity associated with the branch instruction. The circuit and method may further be adapted to calculate the second rate based on the probability factor. The ability to adjust the prefetch rate of a prefetch unit advantageously decreases the number of memory transactions, thereby decreasing the power consumption of a processing unit.

System, circuit, and method for adjusting the prefetch instruction rate of a prefetch unit

A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.

Circuit and method for improving instruction fetch time from a cache memory device

A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.

System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline

The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may include a semiconductor memory device, a cache memory device and a prefetch unit. The system may also include a memory bus to couple the semiconductor memory device to the prefetch unit. The system may further include a circuit coupled to the memory bus. The circuit may detect a branch instruction within the sequence of instructions, such that the branch instruction may target a loop construct. A circuit may also be contemplated herein. The circuit may include a detector coupled to detect a loop within a sequence of instructions. The circuit may also include one or more counting devices coupled to the detector. A first counting device may count a number of clock cycles associated with a set of instructions within a loop construct. A second counting device may count the number of clock cycles remaining in a loop during the last iteration of the loop. The circuit may further include a logic component coupled to the second counting device, such that the logic component may enable/disable the prefetch unit. A method may further be contemplated herein. The method may include detecting when a set of instructions within a last iteration of a loop may be encountered. The method may also include counting a plurality of clock cycles needed to fetch the set of instructions within the loop. The method may enable the prefetch unit when a remaining number of clock cycles substantially equals the number of clock cycles needed to access a memory device.

Growing community of inventors

Plano, TX, United States of America

Asheesh Kashyap