Intel Corporation

Ashay A Dani

Paul A Koning

Saikumar Jayaraman

Christopher L Rumer

Sabina J Houle

Anna M Prakash

Rajen S Sidhu

James Chris Matayabas, Jr

Carl L Deppisch

Mukul P Renavikar

Edward Rudolph Prack

Thomas John Fitzgerald

Vijay Wakharkar

Mitesh C Patel

Lilia May

Thomas J De Bonis

Srinivasa R Aravamudhan

Jason Jieping Zhang

James C Matayabas

Chang Lin

Sujit Sharan

Kaladhar Radhakrishnan

Daewoong Suh

Ravi S Prasher

Yongki Min

Ajit V Sathe

Scott A Gilbert

Gudbjorg H Oskarsdottir

Martha A Dudek

Malavarayan Sankarasubramanian

Chris Matayabas

Chris Rumer

Beverly J Canham

Salkumar Jayaraman

Chad A Kumaus

A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.

Substrate integrated inductor with composite magnetic resin layer

An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

Package structure to enhance yield of TMI interconnections

Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.

Polymer matrices for polymer solder hybrid materials

Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.

Functional material systems and processes for package-level interconnects

Surface-active dopants are added to a portion of a circuit package before a reflow process to promote wetting and reduce the formation of solder bump bridges. The circuit package has a solder element that electrically connects the circuit package to a substrate. A reflow process is performed to attach the solder element to a pad on the circuit package. During the reflow process, the surface-active dopants diffuse to the surface of the solder element and form an oxide passivation layer on the surface of the solder element.

Substrate metallization and ball attach metallurgy with a novel dopant element

Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.

Heat dissipating device with preselected designed interface for thermal interface materials

An electronic assembly having a microelectronic die, a heat spreader and a heat sink. A first thermal interface material is disposed between the microelectronic die and the heat spreader. A second thermal interface material is disposed between the heat spreader and a heat sink. The first and second interface materials each comprising a phase change polymer, a solderable material and a plurality of thermally conductive non-fusible particles. The solderable material interconnecting the non-fusible particles to form a plurality of columnar structures within the phase change polymer.

Phase change material containing fusible particles as thermally conductive filler

An integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and a method of making an electronic assembly.

Integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and method of making an electronic assembly

A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.

Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same

A method for forming a high thermal conductivity heat sink to IC package interface is disclosed. The method uses reactive getter materials added to a two phase solder system having a phase change temperature that is about the normal operating temperature range of the IC, to bind absorbed and dissolved oxygen in the two phase solder interface material at or near the air to solder surface. Over time this chemical binding action results in an oxide layer at the air to solder surface that slows the rate of oxygen absorption into the solder interface material, and thus reduces the harmful oxidation of the solder to IC package interface and the solder to heat sink interface.

Reactive gettering in phase change solders to inhibit oxidation at contact surfaces

Growing community of inventors

Chandler, AZ, United States of America

Ashay A Dani