Hitachi, Ltd.

Renesas Technology Corp.

Other

Renesas Electronics Corporation

Hitachi Cable, Inc.

Hitachi Ulsi Systems Co., Ltd.

Akita Electronics Systems Co., Ltd.

Asao Nishimura

Akihiro Yaguchi

Makoto Kitano

Kunihiro Tsubosaki

Ichiro Anjoh

Kunihiko Nishi

Akio Hasebe

Ichiro Anjo

Sueo Kawai

Gen Murakami

Hiroshi Hozoji

Hiroyoshi Kokaku

Hideki Tanaka

Hideo Miura

Junichi Saeki

Masanori Segawa

Masahiro Ichitani

Hiroshi Kikuchi

Takashi Yokoyama

Takashi Yamazaki

Kazuyoshi Oshima

Aizo Kaneda

Shozo Nakamura

Isamu Yoshida

Noriyuki Kinjo

Masatsugu Ogata

Syuuji Eguchi

Akira Nagai

Chuichi Miyazaki

Masahiko Ogino

Toshio Miyamoto

Yukiharu Akiyama

Tomoaki Kudaishi

Shuji Eguchi

Ryuji Kohno

Masanori Shibamoto

Tetsuro Matsumoto

Ryosuke Kimoto

Naotaka Tanaka

Toshiya Satoh

Yoshihide Yamaguchi

Takumi Ueno

Tetsurou Matsumoto

Kosuke Inoue

Noriyuki Oroku

Nae Yoneda

Atsushi Kazama

Hiroya Shimizu

Hiroyuki Tenmei

Masashi Horiguchi

Shuji Ikeda

Masaharu Kubo

Kazuyoshi Shiba

Koki Noguchi

Tadanori Segawa

Haruo Akahoshi

Toshiaki Ishii

Ichio Shimizu

Naoya Kanda

Tasao Soga

Shigeharu Tsunoda

Atsuyoshi Koike

Mamoru Mita

Tetsuya Nakatsuka

Hisayuki Kato

Hanae Shimokawa

Toshiharu Ishida

Madoka Minagawa

Hiroaki Okudaira

Kenji Ujiie

Tetsuo Kumazawa

Takamichi Suzuki

Hiroshi Koyama

Masachika Masuda

Hiroyuki Ohta

Mitsuaki Katagiri

Nobutake Tsuyuno

Junichi Arita

Akihiko Iwaya

Mitsuaki Haneda

Takashi Hashimoto

Kazuya Takahashi

Satoshi Nakamura

Takahide Ikeda

Toshiaki Morita

Takao Miwa

Ryoichi Kajiwara

Yoichi Tamaki

Hiroo Masuda

Ryo Haruta

Masahiro Koizumi

Yuji Shirai

Norio Okabe

Takeshi Terasaki

Norio Suzuki

Tamaki Wada

Toshio Sugano

Takahiro Daikoku

Tasuku Shimizu

Shigeo Hattori

Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn&#x2014;Ag&#x2014;Bi alloy solder is applied to an electrode through an Sn&#x2014;Bi alloy layer. The Sn&#x2014;Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn&#x2014;Bi alloy layer thereby obtaining an enough bonding strength.

Pb-free solder-connected structure

In a semiconductor integrated circuit device, testing pads () using a conductive layer, such as relocation wiring layers () are provided just above or in the neighborhood of terminals like bonding pads () used only for probe inspection at which bump electrodes () are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Semiconductor integrated circuit device

Pb-free solder-connected structure and electronic device

Semiconductor integrated circuit device and manufacture thereof

Semiconductor integrated circuit device with a fuse circuit

A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Semiconductor device and manufacturing method thereof

A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

Multi-chip module

The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

Semiconductor integrated circuit device having particular testing pad arrangement

Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor devicecomprising: a semiconductor chipa porous stress relaxing layerprovided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layerprovided on the stress relaxing layer and connected to the electrodes; and external terminalsprovided on the circuit layer; wherein an organic protecting filmis formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chipand the protecting filmare exposed outside on a same plane.

Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device

Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Semiconductor device

A semiconductor device is provided which includes a semiconductor element having power pads for supplying a power potential, ground pads for supplying a ground potential, and signal pads for inputting and outputting a signal, all of which are formed on one main surface thereof. Power bumps for outside connection are connected with the power pad by power wiring sections, ground bumps for outside connection are connected with the ground pad by ground wiring sections, and signal bumps for outside connection are connected with the signal pad by signal wiring sections. The power wiring sections or the ground wiring sections are respectively located adjacently on both sides of the signal wiring sections and the power wiring sections are respectively located adjacently on sides of the ground wiring sections.

The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

Memory-Module with an increased density for mounting semiconductor chips

Growing community of inventors

Kokubunji, Japan

Asao Nishimura