Freescale Semiconductor,inc.

Nxp USA, Inc.

Asanga H Perera

Sung-Taeg Kang

Cheong Min Hong

Jane A Yater

Craig T Swift

Byoung W Min

Mark Douglas Hall

Ko-Min Chang

Tushar Praful Merchant

Craig Allan Cavins

A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (-) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions () and to form control terminal electrodes (A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

Nanosheet transistors with reduced source/drain resistance and associated method of manufacture

A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. The devices also includes a control gate adjacent the select gate, a charge storage layer located between the select gate and the control gate and between the control gate and the substrate, and an isolation region over the bottom portion of the select gate and between the top sidewall of the select gate and the charge storage layer. The bottom sidewall of the bottom portion extends to the charge storage layer.

Split-gate non-volatile memory (NVM) cell and method therefor

A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), a middle gate dielectric layer () formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack () formed with one or more low-k gate oxide layers (), where each DGO transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), and a middle gate dielectric layer () formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), and a base oxide layer () formed with one or more low-k gate oxide layers.

Method of forming different voltage devices with high-k metal gate

A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.

Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor

A process integration is disclosed for fabricating non-volatile memory (NVM) cells (--) on a first flash cell substrate area () which are encapsulated in one or more planar dielectric layers () prior to forming an elevated substrate () on a second CMOS transistor area () on which high-k metal gate electrodes (--) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates

A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

Integrated split gate non-volatile memory cell and logic device

Method of forming different voltage devices with high-K metal gate

Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.

Methods and structures for charge storage isolation in split-gate memory arrays

A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.

Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology

A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.

Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology

A method of making a split gate non-volatile memory (NVM) using a substrate includes etching a recess into an isolation region of an NVM region of the substrate and depositing a conductive layer and a capping layer. A select gate and a control gate are formed in the NVM region, and a dummy gate is formed in a logic region of the substrate. A portion of the capping layer is removed and a salicide block bi-layer is deposited and patterned to form a first opening that exposes a contact portion of the conductive layer over the recess. A silicided region is formed on the contact portion. The substrate is planarized to expose the dummy gate, which is replaced with a metal gate. A second opening is etched through a first interlayer dielectric deposited over the substrate to the silicided region. Contact metal is deposited into the second opening.

A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.

Integrated split gate non-volatile memory cell and logic structure

A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates () on a first substrate area () which are encapsulated in one or more planar dielectric layers () prior to forming in-laid high-k metal select gates and CMOS transistor gates () in first and second substrate areas () using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Nonvolatile memory bitcell with inlaid high k metal select gate

A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates (), charge storage layers (), inlaid control gates (), and inlaid control gate contact regions ().

Method of gate strapping in split-gate memory cell with inlaid gate

A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.

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West Lake Hills, TX, United States of America

Asanga H Perera