Matsushita Electric Industrial Co., Ltd.

Asako Miyoshi

Masayoshi Nakayama

Junichi Kato

Seiji Yamahira

Takao Ozeki

Shinichi Hatakeyama

A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.

Nonvolatile semiconductor storage apparatus and method of driving the same

A switch section connects a first wire line aSL to the gate of a first memory transistorand the source of a second memory transistorand a second wire line bSL to the source of the first memory transistorand the gate of the second memory transistorwhen first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistorand the gate of the second memory transistorand the second wire line bSL to the gate of the first memory transistorand the source of the second memory transistorwhen second type data is to be written into a memory cell.

Growing community of inventors

Shiga, Japan

Asako Miyoshi