Apple Inc.

Asaf Landau

Yonathan Tate

Tomer Ish-Shalom

Naftali Sommer

Micha Anholt

Moti Teitel

Armand Chocron

An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

Iterative decoding with early termination criterion that permits errors in redundancy part

An apparatus includes an interface, main and secondary processing modules, and circuitry. The interface is configured to receive input data to be processed in accordance with a GLDPC code defined by a parity-check-matrix including multiple sub-matrices, each sub-matrix including a main diagonal and one or more secondary diagonals, and each of the main and secondary diagonals includes N respective block matrices. The main processing module is configured to calculate N first partial syndromes based on the input data and on the block matrices of the main diagonals. The secondary processing module is configured to calculate N second partial syndromes based on the input data and on the block matrices of the secondary diagonals. The circuitry is configured to produce N syndromes by respectively combining the N first partial syndromes with the N second partial syndromes, and to encode or decode the input data, based on the N syndromes.

Efficient syndrome calculation in processing a GLDPC code

A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.

On-the-fly evaluation of the number of errors corrected in iterative ECC decoding

A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values. . . L&#x2212;1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

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Modiin, Israel

Asaf Landau