Applied Micro Circuits Corporation

Sun Microsystems, Inc.

Net Navigation Systems, LLC

Other

Broadcom Corporation

Asad Khamisy

Alexander Joffe

Michael Lau

Andrew Li

Israel Cidon

Raphael J Rom

Moshe Sidi

Phanindra Jujjavarapu

Man-Tung Tony Hsiao

Puneet Agarwal

Bruce Hui Kwan

Clifford James Buckley

Shree Murthy

Don Hoffman

Logic (also called 'synchronizing logic') in a co-processor (that provides an interface to memory) receives a signal (called a 'declaration') from each of a number of tasks, based on an initial determination of one or more paths (also called &#x201c;code paths&#x201d;) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called &#x201c;disabled&#x201d; task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called &#x201c;needy&#x201d; tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Logic for synchronizing multiple tasks

A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Programmable queuing

Logic for synchronizing multiple tasks at multiple locations in an instruction stream

Programmable queuing instruction set

Instruction set for programmable queuing

A network device and method include token buckets, each token bucket associated with one of clients and virtual ports and configured to process information based on a predefined bandwidth and a strict priority/weighted deficit round robin. A maximum rate shaper module and a minimum rate meter module shape and meter whether any of the clients or virtual ports have exceeded a predefined threshold. A scheduler is configured to schedule services of the clients and to calculate a new bandwidth allocation for at least one of the clients or virtual ports when the at least one of the clients or virtual ports has exceeded the predefined threshold, the new bandwidth allocation replacing the predefined bandwidth and being proportional to the predefined bandwidth for each of the clients or virtual ports.

Hierarchical queue shaping

This disclosure relates to communications among processors, coprocessors and memory. Specifically, a method and apparatus provide a single-cycle instruction ('store-and-load') that stores a command to a co-processor to atomically process data and that loads resultant processed data.

Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller

Logic (also called 're-ordering semaphore') issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphore release between any two semaphore grants. There is no limit on the duration between a semaphore grant and a semaphore release, so that a task that receives a semaphore grant can use the shared resource for any length of time. In one embodiment, each request is associated with a number indicative of the order in which grants are to be issued, and the re-ordering semaphore uses this number in deciding which request is to be granted. The number can be a sequence number that is indicative of the order of arrival of packets that generated the requests.

Shared resource access via declarations that contain a sequence number of a packet

A co-processor (also called 'memory co-processor') provides an interface to a memory, by executing instructions on data held in the memory. The co-processor uses a specified address to fetch data from memory, performs a specified instruction (such as incrementing a counter or policing) on the data to obtain modified data, and writes the modified data back to memory at the same address. Depending on the embodiment, the memory co-processor may include a first buffer for holding instructions that may be received back to back, in successive clock cycles. Instead of or in addition to the first buffer, the memory co-processor may include a second buffer for holding data to be written to memory back to back, in successive clock cycles. In some embodiments, the memory co-processor also receives (and maintains in local storage) the identity of a task that generates the specified instruction, so that the same cask may be awakened after the instruction has been executed.

Memory co-processor for a multi-tasking system

A multi-layer network element for forwarding received packets from an input port to one or more output ports with quality of service. When output queues exceed or meet a threshold value below the queue's capacity packets are ramdomly discarded. When the queue becomes full, the network element determines which flow caused the queue to overflow. The priority of that flow is lowered. In a multicast packet, the packet may have different priorities at each output port. Scheduling of multiple output queues at each output port uses a weight round robin approach that allocates a weight portion of packets to transmit at each time interval. A packet is not interrupted during its transmission, even if the weight portion is met during a packet's transmission. The excess number of bytes transmited as a result of not interrupting the packet are accounted for in the next round.

System and method for a quality of service in a multi-layer network

An efficient, cost effective method and apparatus for performing resource allocation of available bit rate (ABR) virtual circuit (VC) in an asynchronous transfer mode (ATM) network includes an explicit rate switch process performed at at least one switch of an ABR VC. The process provides a fast and more accurate computation of the number of active VCs in an ATM network. Furthermore, the fair share allocation is calculated at the switch in a way that is efficient and lends itself easily to implementation in hardware. For example, in one embodiment, the fair share is implemented using a series of counters and registers controlled by a state machine. This simple hardware implementation enables fast convergence to a current final state so that timely accurate resource utilization and allocation to the ABR VCs can be determined.

Growing community of inventors

Fremont, CA, United States of America

Asad Khamisy