Intel Corporation

Asad Azam

Amit Kumar Srivastava

R Selvakumar Raja Gopal

Vincent J Zimmer

Rajaram Regupathy

Enrico David Carrieri

Subrata Banik

Rajesh Bhaskar

Rao Jagannadha Rapeta

Mikal Hunsaker

Riccardo Mariani

Jagannadha Rao Rapeta

Nabajit Deka

Kaitlyn Chen

Sreejit Chakravarty

Zhenyu Zhu

Mark T Feuerstraeter

Rajesh Banginwar

Jenny Pelner

Jia Jun Lee

Dhinesh Sasidaran

Navtej Singh

Roger May

Prashanth R Gadila

Maulik V Vaghela

Dhinesh A/l Sasidaran

Wenjun Zhang

Maulik Vaghela

Jenny M Pelner

A data processing system comprises a processing core to execute a basic input/output system (BIOS) as part of a boot process. The data processing system also comprises static random-access memory (SRAM) in communication with the processing core. The data processing system also comprises a pre-BIOS component in communication with the SRAM. The pre-BIOS component is configured to execute a pre-BIOS block before the processing core begins executing the BIOS. The pre-BIOS block, when executed by the pre-BIOS component, causes the pre-BIOS component to (a) initialize the pre-BIOS component, (b) measure an amount of time taken to initialize the pre-BIOS component, and (c) save the measured amount of time to the SRAM as a pre-BIOS boot-time record. Other embodiments are described and claimed.

Technology to measure boot activity before a processor enters a working state

Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process

Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

Single chip multi-die architecture having safety-compliant cross-monitoring capability

Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

Boot process for early display initialization and visualization

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

Scalable infield scan coverage for multi-chip module for functional safety mission application

The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

Methods, systems and apparatus for in-field testing for generic diagnostic components

Various systems and methods for implementing secure system-on-chip (SoC) debugging are described herein. A method of providing secure system-on-a-chip (SoC) debugging, comprises: receiving, from a remote host at a debug companion circuit, a debug initiation request to initiate a debugging session with an SoC associated with the debug companion circuit; encrypting, at the debug companion circuit, a debug handshake command; transmitting the debug handshake command to the SoC from the debug companion circuit, wherein the SoC is configured to authenticate the debug companion circuit, and configure intellectual property (IP) blocks on the SoC to expose debug data to the debug companion circuit in response to authenticating the debug companion circuit; and managing a secure connection with the SoC to obtain debug data and report the debug data to the remote host.

Secure external SoC debugging

The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

Methods, systems and apparatus for dynamic temperature aware functional safety

Methods and apparatus relating to functional safety critical audio system for autonomous and industrial applications are described. In an embodiment, safety island logic circuitry transmits an enable signal to cause initiation of a functional safety test for an audio component in a vehicle. Audio processing logic circuitry receives the enable signal and causes activation of power amplifier logic circuitry, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal. The audio component includes a Parametric Acoustic Array (PAA) transducer. Other embodiments are also disclosed and claimed.

Functional safety critical audio system for autonomous and industrial applications

Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

Tunneling functional safety communications over an enhanced serial peripheral interface

Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.

Hardware-based local-state retention fault detection

An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

SoC architecture to integrate with one out of two diagnostics platforms

An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.

Aging tolerant system design using silicon resource utilization

Technologies for built-in self-testing of a memory array using error detection and correction code knowledge include identifying data errors between pseudo random data written to the memory array and the data read back from the memory array and ignoring those data errors determined to be correctable. The data errors may be determined to be correctable if an error corrector circuit can correct those errors or if the number of errors per memory chuck is less than a number of errors correctable by the error correct circuit.

Growing community of inventors

Folsom, CA, United States of America

Asad Azam