Oracle International Corporation

Intel Corporation

Oracle America, Inc.

Magma Design Automation, Inc.

Google Inc.

Sun Microsystems, Inc.

Meta Platforms, Inc.

Microsoft Technology Licensing, LLC

Synopsys, Inc.

Circuit Semantics, Inc.

Arvind Srinivasan

Bjorn Dag Johnsen

Shimon Muller

Marcelino M Dignum

Brian Manula

Robert G Southworth

Haroon Chaudhri

Bartosz Bogdanski

Rahoul Puri

Carlos Alexander Castil

Ajoy Siddabathuni

Samit Chaudhuri

Yunjian (William) Jiang

Robert J Anderson

Ben-Zion Friedman

Mrittika Ganguli

David Arditti Ilitzky

Bjørn Dag Johnsen

Helia A Naeimi

Elisa Rodrigues

Adrian J Isles

Karl S Papadantonakis

Yinghua Li

Partha Das

Joy Banerjee

Line Holen

Lawrence Llewelyn Butcher

Simoni Ben-Michael

Daniel Daly

Bongjin Jung

Ramakrishna Huggahalli

Edward Knapp

Jonathan A Dama

Jonathan Philip Levine

Tony Hurson

Thai Duong

Roberto Penaranda Cebrian

Malek Musleh

Jyotirmaya Akkad

Christopher H Elving

Adam Conyers

Hemanth Krishnan

John Greth

Samuel Thomas Denton

Francesc Guim Bernat

Eliezer Tamir

Hung Phi Nguyen

Scott P Dubal

James Gregory Hanko

Parthasarathy Sarangam

Eliel Louzoun

Alan T Ruberg

John E Watkins

Todd M Rimmer

Yadong Li

Anjali Singhai Jain

Slawomir Putyrski

Harikrishna Madadi Reddy

Ola Torudbakken

Donald Wood

Nrupal R Jani

Anjaneya Reddy Chagam Reddy

Mark Debbage

Brian S Hausauer

James Earl McCormick, Jr

Nisheeth Srivastava

Naader Hasani

Michael F Speer

Ashay Narsale

Mika Nystroem

Gaspar Mora Porta

Pankaj Kansal

Marc Whitney Schneider

Zhong Xu

Murthy Chintalapati

Duane Northcutt

Namrata Limaye

Basant Kukreja

Sivakumar Munnangi

Adam Leftik

Krutibas Biswal

Cheolmin Park

Jerry Wall

Allister Alemania

Alexandre Zavorine

Gargi Saha

Sunil Ahluwalia

Suyog Kulkarni

Lev Faerman

Akeem Abodunrin

David Andreas Sidler

Michael E Duboce

Satyanarayana Simha

Saranga P Pogula

Louise Y Yeung

Sriram Natarajan

Stephen Mark Johnson

Jim McCormick

Shipra Malhotra

A system for facilitating RDMA transmit flow scheduling and pacing is disclosed. The system may determine a set of groups. The groups may be associated with a range of transmission rates. The system may determine a transmission rate of a queue pair. The system may assign the QP to a first group of the set of groups. The transmission rate of the QP may be within the range of transmission rates of the first group. The system may determine an available QP of at least one group from the set of groups. The system may schedule transmission, by an arbiter, of the available QP. The system may transmit, by the arbiter, a message associated with the available QP.

RDMA transmit flow scheduling and pacing scheme for congestion management in high-performance AI/ML networks

Examples described herein relate to a Transport Layer Security (TLS) offload engine to: based on detection of encrypted data unassociated with a previously detected data header: search for one or more data headers; identify at least two candidate data headers for validation; and based on receipt of an indication that the at least two candidate data headers are valid, perform decryption of received data in one or more packets. In some examples, the TLS offload engine is to: based on receipt of an indication that one or more of the at least two candidate data headers is not a valid header, search for two or more other candidate data headers.

Offload of decryption operations

Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

Reliable transport architecture

Examples described herein relate to an interface that is to receive data for transmission and based on indication of failure of receipt of one or more packets that carry segments of the data, cause re-transmission of solely one or more of the multiple packets that comprise a segment of the data referenced by the indication of failure of receipt of one or more packets. In some examples, the interface is to encrypt the data using an encryption engine and to segment the data for transmission using one or more packets. In some examples, the interface is to receive the data and an indication of which segment of the data to re-transmit; encrypt the data; segment the encrypted data into one or more packets; and based on the indication of which segment of the data to re-transmit, transmit solely one or more of the multiple packets that comprise a segment of the data referenced by the indication of failure of receipt of one or more packets.

Transport layer security offload to a network interface

System and method for supporting scalable bitmap based P_Key table in a high performance computing environment. A method can provide, at least one subnet comprising one or more switches, a plurality of host channel adapters, and a plurality of end nodes. The method can associate the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value. The method can associate each of the one or more switches with a bitmap based P_Key table of a plurality of bitmap based P_Key tables. The method can associate each of the host channel adapters with a bitmap based P_Key table of the plurality of bitmap based P_Key tables.

System and method for supporting scalable bit map based P_Key table in a high performance computing environment

Methods for improving end-to-end congestion reaction using adaptive routing and congestion-hint based throttling for IP-routed datacenter networks and associated apparatus. In connection with forwarding packets between sending and receiving endpoints coupled to one or more networks, one or more network switches are configured to detect current or approaching congestion conditions, generate congestion notification packets (CNPs), and return the CNPs to sending endpoints. The CNPs may be routed using one or more adaptive routing mechanisms to forward the CNPs along non-congested paths or may be forwarded along a fastest path to a sender. The CNPs further may comprise meta-data including a flow identifier associated with a packet sent from an endpoint, a congestion level for the flow, and a timestamp. CNPs may comprise unreliable datagrams that may be received out-of-order, with the timestamps being used to determine whether CNPs should be disregarded at a switch along the forwarding path to the sending endpoint or at the sending endpoint. Endpoint network interfaces implement a congestion-CNP table storing entries associating congested flows with congestion levels.

Improving end-to-end congestion reaction using adaptive routing and congestion-hint based throttling for IP-routed datacenter networks

A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.

Chip-to-chip interconnect with a layered communication architecture

Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.

Dynamic virtual cut-through and dynamic fabric bandwidth allocation between virtual cut-through and store-and-forward traffic

System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.

System and method for allowing multiple global identifier (GID) subnet prefix values concurrently for incoming packet processing in a high performance computing environment

Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

Maintaining bandwidth utilization in the presence of packet drops

Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.

Multi-path packet descriptor delivery scheme

Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.

Shared memory mesh for switching

A transmitter can manage when a transmit queue is permitted to transmit and an amount of data permitted to be transmitted. After a transmit queue is permitted to transmit, the transmit queue can be placed in a sleep state if the transmit queue has exceeded its permitted data transmission quota. The wake time of the transmit queue can be scheduled based on a token accumulation rate for the transmit queue. The token accumulation rate can be increased if the transmit queue has other data to transmit after the data transmission. The token accumulation rate can be decreased if the transmit does not have other data to transmit.

Techniques to manage data transmissions

At a network-connected device, congestion at an egress queue can be detected. A potential source of congestion can be identified based on characteristics of a packet that caused the egress queue to become congested. The source of congestion can be a congestion group of transmitters. A group congestion message can be sent to the group of transmitters. The message can identify the packet that caused the egress queue to become congested. Transmitters can respond to the message by reducing their peak transmission rate.

Techniques to reduce network congestion

A switch or network interface can detect congestion caused by a flow of packets. The switch or network interface can generate a congestion hint packet and send the congestion hint packet directly to a source transmitter of the flow of packets that caused the congestion. The congestion hint packet can include information that the source transmitter can use to determine a remedial action to attempt to alleviate or stop congestion at the switch or network interface. For example, the transmitter can reduce a transmit rate of the flow of packets and/or select another route for the flow of packets. Some or all switches or network interfaces between the source transmitter and a destination endpoint can employ flow differentiation whereby a queue is selected to accommodate for a flow's sensitivity to latency.

Techniques for congestion management in a network

Growing community of inventors

San Jose, CA, United States of America

Arvind Srinivasan