Texas Instruments Corporation

Arvind Sridhar

Jayawardan Janardhanan

Sinjeet Parekh

Christopher Andrew Schell

Makram Mounzer Mansour

Khang Duy Nguyen

Eric Paul Lindgren

Timothy Paul Toroni

Robert Charles Farrow, Jr

Valerie Way Chang

Brandon Micah Hoppe

Dean Kumar Banerjee

A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Phase cancellation in a phase-locked loop

A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Corrupted clock detection circuit for a phase-locked loop

A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.

Crystal oscillator offset trim in a phase-locked loop

A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an indication of an output clock frequency. The tool also detects selection by the user of a soft control and, as a result of detecting selection of the soft control, generates a plurality of clock tree solutions. The tool further causes a graphical form of a highlighted one of the clock tree solutions to be displayed in a second window of the GUI. An algorithm for generating the various clock tree solutions is also disclosed.

Clock tree design

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Issaquah, WA, United States of America

Arvind Sridhar