Intel Corporation

Freescale Semiconductor,inc.

Arvind Raman

Ashish V Choubal

Vedvyas Shanbhogue

Muhammad M Khellah

Charles Augustine

Arvind Mandhani

Ajaya V Durg

Kalyan Muthukumar

Jeff Huxel

Sundar Ramani

Samudyatha Chakki

Wei Ey Li

Sanjoy K Mondal

Jeffrey G Wiedemeier

Feroze Merchant

Aswin Ramachandran

Karthik Subramanian

Abdullah Afzal

Krishnakumar Ganapathy

Krishnakanth Venkata Sistla

Alexander Gendler

Hector Adrian Sanchez

Vivek Garg

Dean A Mulla

Eric J DeHaemer

James Steven Burns

James D Allen

Guy G Sotomayor

Gayathri Bhagavatheeswaran

Pascal Meinerzhagen

Johan G Van De Groenendaal

Joseph Gergen

Suyoung Bang

Rahul Agrawal

Ravi Gupta

A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

Software visible and controllable lock-stepping with configurable logical processor granularities

Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

Unified retention and wake-up clamp apparatus and method

An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

All-digital closed loop voltage generator

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Selecting a low power state based on cache flush latency determination

In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

System, apparatus and method for in-field self testing in a diagnostic sleep state

An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

Low power retention flip-flop with level-sensitive scan circuitry

Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

Technologies for managing power during an activation cycle

In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

Controlling telemetry data communication in a processor

A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICC). By reducing the maximum current dissipation, the system cost can be reduced as a less expensive power delivery system is required in one embodiment of the invention.

Method and system for run-time reallocation of leakage current and dynamic power supply current

A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.

Phase locked loop device and method thereof

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Austin, TX, United States of America

Arvind Raman