Intel Corporation

Amazon Technologies, Inc.

Arvind Mandhani

Mahesh U Wagh

Ken Shoemaker

Madhu S Athreya

Woojong Han

Shreekant S Thakkar

Bruce L Fleming

Durgesh Srivastava

Ticky Thakkar

Ashish V Choubal

Ajaya V Durg

Kalyan Muthukumar

Arvind Raman

Kiran A Padwekar

Sundar Ramani

Tariq Afzal

Samudyatha Chakki

Achmed Rumi Zahir

Hans Edward Birch-Jensen

Dibyendu Nandy

Ambika Pajjuri

Rangaprabhu Parthasarathy

Satish B Acharya

Snehal G Joshi

Dhananjay Motwani

Uttam K Sengupta

Uma M Gadamsetty

Pushkaraksha Gejji

Shane D Wall

Kiran Padweka

Shiva Navab

Described herein is a neural network accelerator (NNA) with reconfigurable memory resources for forming a set of local memory buffers comprising at least one activation buffer, at least one weight buffer, and at least one output buffer. The NNA supports a plurality of predefined memory configurations that are optimized for maximizing throughput and reducing overall power consumption in different types of neural networks. The memory configurations differ with respect to at least one of a total amount of activation, weight, or output buffer memory, or a total number of activation, weight, or output buffers. Depending on which type of neural network is being executed and the memory behavior of the specific neural network, a memory configuration can be selected accordingly.

Neural network accelerator with reconfigurable memory

Described herein is a neural network accelerator (NNA) with a decompression unit that can be configured to perform multiple types of decompression. The decompression may include a separate subunit for each decompression type. The subunits can be coupled to form a pipeline in which partially decompressed results generated by one subunit are input for further decompression by another subunit. Depending on which types of compression were applied to incoming data, any number of the subunits may be used to produce a decompressed output. In some embodiments, the decompression unit is configured to decompress data that has been compressed using a zero value compression scheme, a shared value compression scheme, or both. The NNA can also include a compression unit implemented in a manner similar to that of the decompression unit.

Decompression and compression of neural network data using different compression schemes

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Selecting a low power state based on cache flush latency determination

This disclosure describes, in part, techniques for implementing voice-enabled devices in vehicle environments to facilitate voice interaction with vehicle computing devices. Due to the differing communication capabilities of existing vehicle computing devices, the techniques described herein describe different communication topologies for facilitating voice interaction with the vehicle computing devices. In some examples, the voice-enabled device may be communicatively coupled to a user device, which may communicate with a remote speech-processing system to determine and perform operations responsive to the voice commands, such as conducting phone calls using loudspeakers of the vehicle computing device, streaming music to the vehicle computing device, and so forth. In this way, the communication topologies between the voice-enabled computing device, the vehicle computing device, and the user device provide for voice control of vehicle computing devices which may otherwise be unable to be controlled by voice commands.

Architectures and topologies for vehicle-based, voice-controlled devices

An echo cancellation system that synchronizes output audio data with input audio data in a heterogeneous system. The system may increment a counter as outgoing audio frames are sent to a digital-to-analog converter in a speaker. As incoming audio frames are received by an analog-to-digital converter in a microphone, the system may copy contents of the counter into the incoming audio frames. Based on the contents of the counter, the incoming audio frames may be associated with corresponding outgoing audio frames. After synchronizing the incoming audio frames and the outgoing audio frames, the system may perform Acoustic Echo Cancellation by removing the outgoing audio frames from the incoming audio frames.

Synchronization of inbound and outbound audio in a heterogeneous echo cancellation system

Embodiments of a method and apparatus are described for operating a mobile computing device in different modes using different operating systems. An apparatus may comprise, for example, a memory operative to store multiple operating systems, a processor operative to execute the multiple operating systems, an operating system management module operative to select a first operating system when the mobile computing device is in a first mode or a second operating system when the mobile computing device is in a second mode and the mobile computing device is coupled to one or more external devices. Other embodiments are described and claimed.

Method and apparatus for multi-mode mobile computing devices and peripherals

An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Protocol neutral fabric

In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

System, apparatus and method for integrating non-peripheral component interconnect (PCI) resources into a personal computer system

In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

Power management for a system on a chip (SoC)

Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Emulation of an input/output advanced programmable interrupt controller

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San Francisco, CA, United States of America

Arvind Mandhani