International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Arvind M Patel

Robert A Rutledge

Martin Aureliano Hassner

Bum Suck So

Charles Edwin Cox

John Scott Eggenberger

James Lee Hafner

Barry Marshall Trager

Constantin Michael Melas

Ralph Koetter

David T Wang

Mario Blaum

Tarek Makansi

Tetsuya Tamura

Paul H Siegel

Paul Hodges

Brian Harry Marcus

Robert W Anderson

Ralph L Gee

Spencer D Roberts

Abraham M Gindi

Hoan Andrew Au

Wellington C Yu

Richard Michael Hamilton New

Robert L Kwok

Ralf Kotter

Magdi R Orfali

Albert S Su

Kwok W Fung

John J Eige

David Stedman

Jasper A Indelicato

Steven H Souther

A method (and system) of finding byte synchronization over random data, which includes selecting a synchronization symbol maximizing the Hamming distance when slid over itself, and appending the synchronization symbol to random data.

Method and system for synchronization in the presence of thermal asperity

A soft error correction algebraic decoder and an associated method use erasure reliability numbers to derive error locations and values. More specifically, symbol reliability numbers from a maximum likelihood (ML) decoder as well as a parity check success/failure from inner modulation code symbols are combined by a Reed-Solomon decoder in an iterative manner, such that the ratio of erasures to errors is maximized. The soft error correction (ECC) algebraic decoder and associated method decode Reed Solomon codes using a binary code and detector side information. The Reed Solomon codes are optimally suited for use on erasure channels. A threshold adjustment algorithm qualifies candidate erasures based on a detector error filter output as well as modulation code constraint success/failure information, in particular parity check or failure as current modulation codes in disk drive applications use parity checks. This algorithm creates fixed erasure inputs to the Reed Solomon decoder. A complementary soft decoding algorithm of the present invention teaches the use of a key equation solver algorithm that calculates error patterns obtained as a solution to a weighted rational interpolation problem with the weights given by the detector side information.

Soft error correction algebraic decoder

A method and apparatus for ensuring the integrity of data that can detect errors that remain when the data correction scheme fails to correct at least some of the errors, or has added additional errors. Reed-Solomon check symbols are used for error correction and cyclic redundancy check symbols are used to detect the remaining errors. The roots of the generator polynomials used to generate the Reed-Solomon check symbols and the cyclic redundancy check symbols meet a selected subset of a plurality of conditions. The roots are further selected so that the necessary exponentiation may be performed by a combination of exponentiations by powers of two and multiplications. The Reed-Solomon check symbols are generated based on the data portion of the data block. A deterministically altered data stream is generated based on the data portion of the data block and the cyclic redundancy check symbols are generated based on the deterministically altered data stream. The deterministically altered data stream is generated by performing an operation on a symbol of the data portion based on a position of the symbol within a Reed-Solomon codeword.

Method and apparatus for updating cyclic redundancy check information for data storage

Method and apparatus for deterministically altering cyclic redundancy check information for data storage

A method and means for enhancing the error detection and correction capability obtained when a plurality of data byte strings are encoded in a two-level, block-formatted linear code using code word and block-level redundancy. This is accomplished by vector multiplication of N data byte vectors and a nonsingular invertible integration matrix with nonzero minors with order up to B to secure the necessary interleaving among N data byte vectors to form modified data byte vectors. The selected patterns of interleaving ensure single-pass, two-level linear block error correction coding when the modified data vectors are applied to an ECC encoding arrangement. The method and means are parameterized so as to either extend or reduce the number of bursty codewords or subblocks to which the block-level check bytes can be applied. Lastly, a post-encoding process is provided to &ldquo;deinterleave&rdquo; or redistribute the computed codewords into modified codewords such that the data vectors and their codeword check bytes are consistently located in the same codeword with the block-level check bytes are distributed among the first-level codewords.

Method and apparatus for efficient error detection and correction in long byte strings using generalized, integrated, interleaved reed-solomon codewords

A method and means for enhancing the error detection and correction capability obtained when a plurality of data byte strings are encoded in a two-level, block-formatted linear code using codeword and block-level redundancy by logically summing the data byte strings and mapping the logical sum and the data byte strings into counterpart codewords including codeword check bytes in accordance with the same linear error correction code. Next, the codewords are logically summed. The codewords and their logical sum are interleaved in a predetermined pattern prior to being recorded on a storage device or the like. On read back, the codewords of a block and their logical sum are syndrome processed to resolve any identified errors within the correction capability of any single word and any errors within the correction capability of any single word and block-level redundancy, and to provide signal indication when the correction capacity has been exceeded.

Method and means for efficient error detection and correction in long

A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These 'side-samples' contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error. Both side-samples of every pulse are weighted uniformly, independent of data pattern, thereby maximizing available phase information and ensuring the rapid acquisition and convergence of the sampling clock phase.

Digital timing recovery method and apparatus for a coded data channel

To improve data detection reliability in a coded maximum likelihood signal processing channel, two counters count the number of times actual values of linear functions of digital sample values corresponding to one and another preselected data patterns are within m units above and m units below, respectively, a preselected decision boundary used to determine whether detected data corresponding to a coded sequence of runlength limited code is a '1' or a '0'. A difference count has a magnitude and sign denoting difference between counts in the two counters. After N occurrences of each preselected data pattern irrespective of how far from the boundary, the boundary is adjusted upwardly or downwardly, provided the difference count at least equals +S or at most -S, respectively.

Setting optimal boundary thresholds in a decoder for coded signal

Decoder for processing digital sample values corresponding to an incoming read signal representative of coded binary data. Functional expressions of digital sample values are precomputed for a preselected number of sample values ahead of a current sample value. To provide binary decision outputs, preselected functional expressions are compared against binary representations of corresponding thresholds that are conditioned by the sign of a selected functional expression comprising at least one preselected digital sample value. These outputs, the sign of the selected functional expression, the current value and previous value of decoded data, and the current value of detected phase, are all used to determine the next value of decoded data and next value of detected phase. These next values become the current values of decoded data and detected phase for the next clock cycle. The binary representations input to the comparators and the binary decision outputs of the comparators are inverted only if the selected functional expression has a preselected sign.

Prejudging current state in a decoder for coded signal processing

A direct access storage device (DASD) system uses a read/write head having a wide transducer write element and a narrow magneto-resistive read element. In order to avoid mistakenly reading a incompletely erased old data field, the system uses a verification procedure. Data are read at two positions along the data track which are separated by a radial distance D. This distance D is selected to be greater than the width of any incompletely erased data record. If the data read at the two read positions are equal, then the data are deemed to be correct and are sent to a host system.

Error recovery data storage system and method with two position read

A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.

Eight-sample look-ahead for coded signal processing channels

A method for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. A state-dependent sequence detection algorithm includes two groups of appropriate functional expressions of digital sample values, which expressions are identical but offset one sample position from each other. During each iterating step with successive pairs of clock cycles, the value of each expression in the two groups of expressions is precomputed from a preselected number of sample values ahead of a then current sample value; preselected ones of these expression values are compared against an appropriate threshold, which is the same for corresponding expressions of each group, to provide respective binary decision outputs corresponding to each of the two groups; and the current state value then advances to two next successive state values. A pipelined configuration is utilized in which a different number of sample values, greater than said preselected number, is used ahead of the current sample value to allow sufficient time for precomputing said groups of expressions.

High data rate decoding method for coding signal processing channels

Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.

Clock delay trim adjustment with stopping feature for eliminating

A method and apparatus for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. Using a state-dependent sequence detection algorithm appropriate functional expressions of digital sample values are precomputed at each cycle of the digitizing clock for a preselected number of bits ahead of the current bit. Preselected ones of these expressions are compared against corresponding thresholds to provide respective binary decision outputs that, with state values corresponding to the current state, determine state values for the next state and decode one bit of coded binary data at each clock cycle. Programmed values generated for the thresholds may be adaptively modified according to changes in sample values in the incoming analog signal relative to corresponding expected sample values. Different thresholds are used for positive and negative phases of the analog signal shape to accommodate signal shape asymmetry. Because the decoder is programmable, threshold constants at different tracks or bands of tracks in a disk file can be changed to optimize performance at all tracks of the file.

Method and apparatus for processing sample values in a coded signal

A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all subblocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining.

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San Jose, CA, United States of America

Arvind M Patel