Intel Corporation

Qualcomm Incorporated

Hewlett-packard Development Company, L.p.

Mcafee, Inc.

Arvind Krishnaswamy

Koichi Yamada

Can Acar

Ravi L Sahita

David J Sager

Jeffrey J Cook

Robert Paul Turner

Ruchira Sasanka

Jason M Agron

Daniel M Lavery

Jayaram Bobba

Palanivelrajan Rajan Shanmugavelayutham

Abhinav Das

Palanivelra Shanmugavelayutham

Suresh Kumar Venkumahanti

Paul Caprioli

Jiwei Lu

Abhay Kanhere

Richard Senior

Suresh Srinivas

Omar M Shaikh

Charles Joseph Tabony

Muawya M Al-Otoom

Greg William Dalcher

Sundeep Kushwaha

Ashish Venkat

Palanivelrajan R Shanmugavelayutham

Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.

Techniques for instruction perturbation for improved device security

Various embodiments include methods and devices for generating a memory map configured to map virtual addresses of pages to physical addresses, in which pages of a same size are grouped into regions. The embodiments may include adding a first entry for a first additional page to a first region in the memory map, shifting virtual addresses of the first region to accommodate a shift of virtual addresses of the first region allocated for code by a sub-page granular shift amount, mapping shifted virtual addresses of the first entry for the first additional page to physical address mapped to a first lowest shifted virtually addressed page of the first region, and shifting the virtual addresses of the first region allocated for code by a sub-page granular shift amount, in which the virtual addresses of the first region allocated for code partially shift into the first entry for the first additional page.

Increasing address space layout randomization entropy via page remapping and rotations

Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

Techniques for detecting return-oriented programming

A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.

Method and system using exceptions for code specialization in a computer architecture that supports transactions

Technologies for assembling an execution profile of an event are disclosed. The technologies may include monitoring the event for a branch instruction, generating a callback to a security module upon execution of the branch instruction, filtering the callback according to a plurality of event identifiers, and validating a code segment associated with the branch instruction, the code segment including code executed before the branch instruction and code executed after the branch instruction.

Hardware and software execution profiling

A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

Using control flow data structures to direct and track instruction execution

A method of producing a control stack includes: writing a plurality of control information entries into a control stack buffer that is internal to a processor in response to one or more function calls; and in response to the control stack buffer being full and receiving a further function call, writing: the plurality of control information entries to an external memory that is external to the processor; and a further control information entry, corresponding to the further function call, to the control stack buffer.

Authenticated control stacks

Techniques for enforcing flow control of a software program in a processor are provided. An example method according to these techniques includes analyzing program code of the software program to identify a code pointer in the program code, generating an authentication tag based on the code pointer, and modifying the code pointer in the program code with the authentication tag to generate a tagged code pointer.

Code pointer authentication for hardware flow control

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

In an embodiment, a processor includes a binary translation engine to receive a code segment, to generate a binary translation of the code segment, and to store the binary translation in a translation cache, where the binary translation includes at least one policy check routine to be executed during execution of the binary translation on behalf of a security agent. Other embodiments are described and claimed.

Performing security operations using binary translation

This disclosure is directed to binary translator driven program state relocation. In general, a device may protect vulnerable program functions by setting them as non-executable. If an attempt is made to execute a protected program function, the program may trap to a binary translator in the device that may be configured to relocate program state from what has already been established (e.g., on a stack register). Program state may include resources (e.g., memory locations) used by the program during the course of execution. The binary translator may then translate the program into an executable form based on the relocated program state, and may be executed accordingly. Intruding code that attempts to overcome normal program execution and implement hostile operations (e.g., based the program state that is reflected in the stack register) will not function as intended since the relocated program state will cause unexpected results.

Binary translator driven program state relocation

A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.

Memory disambiguation hardware to support software binary translation

A compiled program has an advanced-load instruction and a load-checking atomic section. The load-checking atomic section follows the advanced-load instruction in the compiled program. The advanced-load instruction, when executed, loads a value from a shared memory address. The load-checking atomic section includes a check instruction for checking the validity of the shared memory address.

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San Jose, CA, United States of America

Arvind Krishnaswamy