Advanced Micro Devices Corporation

Fasl LLC

Other

Spansion LLC.

E.i. Dupont De Nemours and Company

Cypress Semiconductor Corporation

Arvind Halliyal

Mark T Ramsbey

Minh Van Ngo

Hidehiko Shiraiwa

Tazrien Kamal

Robert B Ogle

Bhanwar Singh

Nicholas H Tripsas

Jean Y Yang

Ramkumar Subramanian

Rinji Sugino

Jaeyong Park

Joong Jeon

Jeffrey Allan Shields

Jusuke Ogura

Fred T K Cheung

Amir Hossein Jafarpour

Zoran Krivokapic

Dawn M Hopper

George Jonathan Kluth

Kenneth W Au

Angela Tai Hui

Matthew S Buynoski

Michael K Templeton

Kuo-Tung Chang

William George En

Effiong Etukudo Ibok

Wei Zheng

David Keating Foote

Inkuk Kang

Hideki Komori

Bharath Rangarajan

Kenneth Warren Hang

Khoi A Phan

Mark W Randolph

Ning Cheng

Chih-Yuh Yang

Robert A Huertas

Jeff P Erhardt

Emmanuil Lingunis

Pei-Yuan Gao

Steven K Park

Fred Cheung

Tyagamohan Gottipati

Robert Bertram Ogle, Jr

Clarence B Ferguson

Ming-Ren Lin

Huicai Zhong

Cyrus E Tabery

Eric N Paton

Unsoon Kim

Yider Wu

Kashmir S Sahota

Krishnashree Achuthan

Kuo Tung Chang

Roger Harquail French

Wenmei Li

Jean Yee-Mei Yang

Stephen Keetai Park

Jeffrey P Erhardt

Jack F Thomas

Yun Wu

Robert B Clark-Phelps

Lorri P Drozdyk

Wei Zhang

Susan G Kim

Michael J Haun

Jeffery A Shields

Shiraiwa Hidehiko

Nicholas H Tripisas

Farzad Arsania

Minh-Ren Lin

In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO.

Memory devices containing a high-K dielectric layer

A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Buried silicide local interconnect with sidewall spacers and method for making the same

A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed over the interface layer by laser processing. The gate electrode is formed over the substrate and the gate dielectric after the laser processing step, and source/drain regions are formed in the substrate proximate to the gate electrode.

Nitridation of gate oxide by laser processing

A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.

Semiconductor memory with data retention liner

The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by providing a semiconductor substrate having a silicon surface; forming a first oxide layer on the silicon surface; depositing a silicon nitride layer on the first oxide layer; and forming a top oxide layer on the silicon nitride layer, wherein the top oxide layer is formed by an in-situ steam generation oxidation of a surface of the silicon nitride layer. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate FLASH memory device including an ONO structure.

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process

A system for monitoring and controlling the deposition of thin films employed in semiconductor fabrication is provided. The system includes one or more acoustic and/or ultrasonic wave sources, each source directing waves onto one or more thin films deposited on a wafer. Waves reflected from the thin film is collected by a monitoring system, which processes the collected waves. Waves passing through the thin film may similarly be collected by the monitoring system, which processes the collected waves. The collected waves are indicative of the presence of impurities and/or defects in the deposited thin film. The monitoring system analyzes and provides the collected wave data to a processor, which determines whether adjustments to thin film deposition parameters are needed. The system also includes a plurality of thin film deposition devices associated with depositing thin films on the wafer. The processor selectively controls thin film deposition parameters and devices to facilitate regulating deposition.

Scatterometry and acoustic based active control of thin film deposition process

A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is deposited.

Memory with improved charge-trapping dielectric layer

Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

A method of manufacturing an ONO (oxide-nitride-oxide) insulating layer for a flash memory device, the insulating layer including a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein at least one of the first oxide layer, the nitride layer and the second oxide layer are conditioned using laser thermal annealing.

Laser thermal annealing methods for flash memory devices

According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

Memory cell structure having nitride layer with reduced charge loss and method for fabricating same

A SONOS flash memory device, including a semiconductor substrate; an ONO structure formed on the semiconductor substrate, the ONO structure including a bottom oxide layer, a dielectric charge storage layer and a top oxide layer, the bottom oxide layer having a super-stoichiometric oxygen content and an oxygen vacancy content of about 10/cmor less, wherein the bottom oxide layer exhibits a reduced charge leakage relative to a bottom oxide layer having a stoichiometric or sub-stoichiometric oxygen content and a greater number of oxygen vacancies. In one embodiment, the bottom oxide layer has an oxygen vacancy content of substantially zero.

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Growing community of inventors

Cupertino, CA, United States of America

Arvind Halliyal