Nvidia Corporation

Arvind Gopalakrishnan

Jerome Francis Duluk, Jr

Samuel Hammond Duncan

James Leroy Deming

Mark Hairgrove

Robert T George

Cameron Buschardt

Lucien Dunning

John Mashey

Chenghuan Jia

Sherry Cheung

Sachin Satish Idgunji

Naveen Cherukuri

Shailendra Singh

Narayan Kulshrestha

Manas Mandal

Amit Pabalkar

Jonathon Stuart Ramsay Evans

Aniket Naik

Justin Tai

Bardia Zandian

Siddharth Bhargav

Vaibhav Vyas

Apparatuses, systems, and techniques to detect memory errors and isolate or migrate partitions on a parallel processing unit using an application programming interface to facilitate parallel computing, such as CUDA. In at least one embodiment, interrupts are intercepted and processed on a graphics processing unit indicating a memory error for one or more partitions, and a policy is applied to isolate that memory error from other partitions.

Techniques for memory error isolation

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Fault buffer for tracking page faults in unified virtual memory system

Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

Optimal operating point estimator for hardware operating under a shared power/thermal constraint

Fault buffer for resolving page faults in unified virtual memory system

Migration scheme for unified virtual memory system

Common pointers in unified virtual memory system

Page state directory for managing unified virtual memory

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San Jose, CA, United States of America

Arvind Gopalakrishnan