Qualcomm Incorporated

Arvind Chandrasekaran

Brian Matthew Henderson

Jonghae Kim

Shiqun Gu

Ratibor Radojcic

Ryan David Lane

Homyar C Mogul

Mark M Nakamoto

Christine S Hau-Riege

A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors.

Panelized backside processing for thin semiconductors

A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Dual-side interconnected CMOS for stacked integrated circuits

An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided.

Microfabricated pillar fins for thermal management

A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.

Hybrid package construction with wire bond and through silicon vias

An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.

Interconnect sensor for detecting delamination

A process for wafer-to-wafer bonding of a first wafer having a first set of dies of a first die size to a reconstituted wafer of a second set of dies having a second die size different than the first die size. The process includes aligning the second set of dies such that a second set of interconnects on the second set of dies aligns with a first set of interconnects on the first set of dies. The second set of dies includes a spacing between the second set of dies based on parameters of the first set of dies. The process also includes coupling the reconstituted wafer with the first wafer to create a wafer stack.

Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers

A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

Discontinuous thin semiconductor wafer surface features

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Conductive sidewall for microbumps

A passive device having a portion in the package substrate and a portion in the system board such that the portions of the device are electromagnetically coupled. A transformer including inductors in the package substrate and system board electromagnetically coupled across a space between the substrate and board that is surrounded by solder balls coupling the substrate and board. A capacitor including plates in the substrate and board electromagnetically coupled across a space between the substrate and board that is surrounded by solder balls coupling the substrate and board. A core material can at least partially fill the space between the substrate and board. The solder balls surrounding the space can be coupled to ground. Metal shielding can be put in the substrate and/or board surrounding the device. The metal shielding can be coupled to the solder balls. The metal shielding can be coupled to ground.

Passive coupler between package substrate and system board

An electronic system includes a system board and a packaging substrate mounted on the system board. One or more semiconductor dies are mounted on the packaging substrate and coupled to the system board. The system also includes one or more semiconductor die-based packaging interconnects between the system board and the packaging substrate. The semiconductor die-based packaging interconnect has a first face coupled to the system board and a second face coupled to the packaging substrate. Through silicon vias located in the semiconductor die-based packaging interconnect enable communication between the system board and the one or more semiconductor dies. The semiconductor die-based packaging interconnects may include passive devices, active devices, and/or circuitry. For example, the semiconductor die-based packaging interconnect may provide impedance matching, decoupling capacitance, and/or amplifiers for minimizing insertion loss.

Semiconductor die-based packaging interconnect

Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.

Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits

A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.

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San Diego, CA, United States of America

Arvind Chandrasekaran