Intel Corporation

Applied Materials, Inc.

Tahoe Research, Ltd.

Arvind A Kumar

Venkatraman Iyer

Darren S Jue

Rahul R Shah

Vedvyas Shanbhogue

Debendra Das Sharma

Robert G Blankenship

Barnes Cooper

Aleksander Magi

Giuseppe Beppe Raffa

Raj K Ramanujan

Yen-Cheng Liu

Simon P Johnson

Robert J Safranek

Herbert H Hum

Prosenjit Ghosh

Ashish Gupta

Vedaraman Geetha

Bahaa Fahim

Jeffrey Charles Swanson

Aaron T Spink

Fulvio Spagna

Purushottam Goel

Robert H Beers

Jeff Willey

Vivek Paranjape

Sitaraman V Iyer

Marko Bartscherer

William Harry Nale

John R Goles

Hong W Wong

Denica N Larsen

Balaji Vembu

Glen J Anderson

Ren Wang

Mahendra Pakala

Duck Young Kong

Kristoffer Fleming

Meng Shi

Wendy March

Antonio S Cheng

Ned M Smith

Tsung-Yuan Charles Tai

John Charles Weast

Christopher E Cox

Ellie Y Yieh

Glenn J Hinton

Murali Ramadoss

David I Poisner

Per H Hammarlund

James M Okuley

Ajay V Bhatt

Gustavo Fricke

John J Valavi

Johan G Van De Groenendaal

Vincent J Zimmer

David M Durham

Michael A Rothman

Ravi L Sahita

Mohan J Kumar

Anchuan Wang

James A McCall

Rahul Khanna

Alexander W Min

Xue Yang

Shao-Wen Yang

Jr-Shian Tsai

Bill Nale

John Tolle

Zhiming Zhuang

Kunjal ShyamKumar Parikh

Sony Varghese

Nilesh V Shah

Yan Chen

Lei Yang

Julio Cesar Zamora Esquivel

Zihui Li

Patrick G Kutch

Nagasubramanian Gurumoorthy

Michael W Rhodehamel

Amit S Baxi

David M Putzolu

Rahul C Shah

Ke Han

Shantanu Dattatraya Kulkarni

Jun Jiang

James R Trethewey

Scott D Hahn

Priya Rajagopal

Vincent S Mageshkumar

Thanunathan Rangarajan

Duncan Glendinning

Carey W Smith

David J O'Shea

Chai Huat Gan

Anthony Kozaczuk

Greeshma Pisharody

Santanu Chaudhuri

Narayanan Natarajan

Christopher R Carlson

In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.

Reference voltage adjustment per path for high speed memory signaling

Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA function implemented on a memory module (e.g., DDR5 SDRAM DIMM) to obtain a first set of optimized DCA code settings. The first set of optimized DCA code settings are then used as initial settings for the Advance DCA training algorithm to further optimize the DCA code settings for QCLK, IBQCLK, and QBCLK. A similar technical may be employed to reduce duty cycle error and jitter for DQ signals.

Duty cycle adjuster optimization training algorithm to minimize the jitter associated with DDR5 DRAM transmitter

A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

Apparatus, system and method to detect and improve an input clock performance of a memory device

Systems and methods for multi-modal user device authentication are disclosed. An example electronic device includes a first sensor, a microphone, a first camera, and a confidence analyzer to authenticate a subject as the authorized user in response to a user presence detection analyzer detecting a presence of the subject and one or more of (a) an audio data analyzer detecting a voice of an authorized user or (b) an image data analyzer detecting a feature of the authorized user. The example electronic device includes a processor to cause the electronic device to move from a first power state to a second power state in response to the confidence analyzer authenticating the user as the authorized user. The electronic device is to consume a greater amount of power in the second power state than the first power state.

Systems and methods for multi-modal user device authentication

In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.

Reference voltage training per path for high speed memory signaling

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

Methods and apparatus to operate closed-lid portable computers are disclosed. An example portable computer includes a first display on a lid of the portable computer, the first display to be deactivated when the lid is in a closed position; a second display distinct from the first display, the second display to be visible when the lid is in the closed position; instructions; and processor circuitry to execute the instructions to cause activation of the first display in response to a user interaction with the second display while the lid is in the closed position.

Methods and apparatus to operate closed-lid portable computers

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

Replacement channel process for three-dimensional dynamic random access memory

Systems, apparatuses and methods may provide for detecting an identifier communication from a writing implement and transitioning a previously modified interior page of an electronic notepad from a locked state to an unlocked state if the identifier communication corresponds to one or more stored identifiers. Moreover, a plurality of additional interior pages of the electronic notepad may be maintained in the locked state while the previously modified interior page is in the unlocked state.

Unlocking electronic notepads for writing

Computer notebook

Methods and apparatus to operate closed-lid portable computers are disclosed. An example portable compute device includes: a microphone; a speaker; a first camera to face a first direction; and a second camera to face a second direction, the second direction opposite the first direction. The compute device further includes communications circuitry; a first display; a second display separate from the first display; and a hinge to enable the first display to rotate relative to the second display between an open position and a closed position. At least a portion of the second display is capable of being visible when the first display is rotated about the hinge to the closed position. The portion of the second display is multiple times longer in a third direction than in a fourth direction perpendicular to the third direction, the third direction extending parallel to an axis of rotation of the hinge.

An example electronic user device includes memory; instructions; and processor circuitry to execute the instructions to identify a stylus grip pattern indicative of a grip of a user on a stylus based on signal data corresponding to signals output by a sensor of the stylus; select one of a first stylus mode or a second stylus mode for the stylus based on the stylus grip pattern; interpret an interaction between the stylus and the electronic user device based on the selected one of the first stylus mode or the second stylus mode; and cause the electronic user device to respond to the interaction.

Predictive detection of user intent for stylus use

Growing community of inventors

Palo Alto, CA, United States of America

Arvind A Kumar