Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Arup De

Kiran Kumar Gunnam

Pankaj Mehra

Seung-Hwan Song

Brian Walter O'Krafka

Dejan Vucinic

Minghai Qin

Chao Sun

Vidyabhushan Mohan

Apparatuses, systems, methods, and computer program products are disclosed for balanced caching. An input circuit receives a request for data of non-volatile storage. A balancing circuit determines whether to execute a request by directly communicating with one or more of a cache and a non-volatile storage based on a first rate corresponding to the cache and a second rate corresponding to the non-volatile storage. A data access circuit executes a request based on a determination made by a balancing circuit.

Balanced caching between a cache and a non-volatile memory based on rates corresponding to the cache and the non-volatile memory

Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such method includes receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface, performing, at the first SPU, the processing task, and transferring data from the first SPU to a second SPU via an interconnection network, where each of the plurality of SPUs includes a non-volatile memory (NVM) and a processing circuitry configured to perform the processing task.

Systems and methods for offloading processing from a host to storage processing units using an interconnect network

Aspects of the disclosure provide for memory efficient persistent key value store for a solid state device (SSD). The methods and apparatus provide a non-volatile memory (NVM) and a key value store (KVS) processor. The non-volatile memory (NVM) is configured to store a key value data structure. The KVS processor is configured to receive a key value store (KVS) command from a host. The KVS processor is also configured to perform a key value store (KVS) operation on the key value data structure based on the received KVS command. The performing of the key value store (KVS) operation may include using an index structure to process the key value data structure based on the received KVS command. The KVS processor is further configured to provide a response to the host based on the KVS operation.

Memory efficient persistent key-value store for non-volatile memories

A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.

Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

Non-volatile storage system with compute engine to accelerate big data applications

In general, techniques are described by which to provide an interface architecture for storage devices. A storage device comprising non-volatile memory, and a hardware controller may be configured to perform various aspects of the techniques. The hardware controller may be configured to read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hardware controller. The hardware controller may further be configured to send a plurality of commands received from the direct communication channel into a hardware queue, and issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory.

Programmable input/output (PIO) engine interface architecture with direct memory access (DMA) for multi-tagging scheme for storage devices

A system is described that includes a data bus communicatively coupled to a host processor, a graphics processing unit (GPU), and a data storage unit. The GPU is configured to receive instructions from the host processor to perform direct communication over the data bus with the data storage unit. Responsive to receiving instructions to communicate directly with the data storage unit, the GPU will initiate a direct communication channel over the data bus. Once established, a direct communications channel allows the data storage unit and the GPU to directly exchange information and bypass the host CPU and system memory.

Direct interface between graphics processing unit and data storage unit

The embodiments disclosed herein include an interconnection network that is configured to provide data communication between storage processing units. The disclosed interconnection network can be particularly effective when the storage processing units are configured to locally perform scientific computations. The disclosed interconnection network can enable localized, high throughput, and low latency data communication between storage processing units without overloading the host system.

Storage processing unit arrays and methods of use

Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such system includes a host having a processing task, a plurality of storage processing units (SPUs), a host interface configured to enable communications between the host and each of the plurality of SPUs, and an interconnection network coupled to at least two of the plurality of SPUs, where the host is configured to command at least one of the plurality of SPUs to perform the processing task, and command the interconnection network to couple two or more of the plurality of SPUs.

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Milpitas, CA, United States of America

Arup De