Texas Instruments Corporation

Arup Dash

Sabyasachi Sengupta

Sushil Kumar Gupta

Rituparna Mandal

Dibyendu Goswami

An integrated tool which allows layouts for cells to be generated using a combination of synthesis, migration and manual approaches. In an embodiment, a compaction tool of a migration engine/module is used to perform incremental compaction. Various utilities are developed to enable the use of the compaction tool. For example, when using synthesis to generate layout for a new combinational cell, a utility to generate inputs to the migration engine from pre-compaction representation of the synthesis tool is provided according to an aspect of the present invention. Another utility generates a device table indicating the manner in which each component of a pre-existing layout needs to be modified to generate a layout consistent with a target netlist. The device table and the pre-existing layout can be provided as an input to the migration engine to perform incremental compaction.

Reducing cell library development cycle time

A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback driver circuits minimize (prevent) an amount of time both the NMOS and PMOS transistors are in an ON state at the same time, thereby reducing short circuit power (i.e., the power dissipated if both the PMOS and NMOS transistors are in an on state). In addition, as the two feedback driver circuits do not contain common input inverter circuits, the short circuit power is further reduced.

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Bengaluru, India

Arup Dash