Sk Hynix Memory Solutions Inc.

Skhynix Inc.

Arunkumar Subramanian

Jason Bellorado

Lingqi Zeng

Xiangyu Tang

Frederick K H Lee

Zheng Wu

Ameen Aslam

Suneel Indupuru

Naveen Kumar

Marcus Marrow

A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.

Reading and writing to NAND flash memories using charge constrained codes

A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value.

Generating soft read values using multiple reads and/or bins

A workload level associated with an expandable data buffer is determined, where the expandable data buffer and an expandable mapping table cache are stored in internal memory and the expandable mapping table cache is used to store a portion of a mapping table that is stored on external storage. An amount of internal memory allocated to the expandable data buffer and an amount of internal memory allocated to the expandable mapping table cache are adjusted based at least in part on the workload level.

Workload-based adjustable cache size

An instruction to write data to a write logical address is received where the write logical address is a member of a group of one or more logical addresses. It is determined if data associated with any of the logical addresses in the group of logical addresses has been written to any of a plurality of open groups of locations. If so, the data is written to the open group of locations to which data from the group of logical addresses has already been written to. If not, an open group of locations to write to is selected from the plurality of open groups of locations.

Selection of an open block in solid state storage systems with multiple open blocks

One or more source locations in a group of solid state storage cells on which garbage collection is to be performed are stored in a garbage collection queue. A garbage collection speed is determined, including by: analyzing one or more source locations stored in the garbage collection queue; determining a look-ahead metric, wherein the look-ahead metric comprises an anticipated amount of freed up storage associated with the analyzed source locations; and determining the garbage collection speed based at least in part on the look-ahead metric. One or more garbage collection operations are performed interleaved with one or more host operations, wherein the ratio of garbage collection operations to host operations is based at least in part on the garbage collection speed.

Look-ahead garbage collection for NAND flash based storage

A locality associated with a read request is identified based at least in part on a read address included in the read request. A predicted read address is generated based at least in part on the locality. It is decided whether to permit the predicted read address to be prefetched; in the event it is decided to permit the predicted read address to be prefetched, data from the predicted read address is prefetched and the prefetched data is stored in a prefetch cache.

Prefetch with localities and performance monitoring

A group of one or more solid state storage cells is programmed. A predetermined amount of time after the group of solid state storage cells is programmed, the group of solid state storage cells is read to obtain read data. Error correction decoding is performed on the read data and the group of solid state storage cells is assessed for wear related degradation based at least in part on the error correction decoding.

Check after write for assessing wear related degradation in solid state storage

A set of one or more component syndromes associated with a turbo product code (TPC) codeword is obtained from a component syndrome buffer. Component decoding is performed on the set of one or more component syndromes.

Syndrome tables for decoding turbo-product codes

A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration of the read threshold voltage to obtain a second characteristic. A third iteration of the read threshold voltage is generated using the first and second characteristics. A read is performed using the third iteration of the read threshold voltage to obtain a third characteristic. It is determined if the third characteristic is one of the two characteristics closest to a stored characteristic. If so, a fourth iteration of the read threshold voltage is generated using the two closest characteristics.

Finding optimal read thresholds and related voltages for solid state memory

A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. The second bit position of the cell is read for a second time, including by setting the first read threshold to a third value and setting the second read threshold to a fourth value. A new value for the first read threshold and for the second read threshold is generated using the sorting bit, the first read, and the second read.

Generating read thresholds using gradient descent and without side information

A system and method for determining soft read data for a group of cells in a nonvolatile flash memory are disclosed. An expected value representative of a plurality of stored values in a group of cells is obtained. A measured value representative of the plurality of stored values in the group of cells is obtained, based on a single read to the group of cells. A soft read data for the group of cells is determined based at least in part on the expected value and the measured value. The expected and measured values may include at least one of a number of 0s, a number of 1s, a ratio of 0s to 1s or a ratio of 1s to 0s. A reliability for a bit i may be obtained using a one-step majority logic decoder, and a threshold reliability may be used when determining the soft read data.

Method and system for generating soft-information after a single read in NAND flash using expected and measured values

A victim group of one or more cells is read using a first read threshold to obtain a first raw read which includes one or more values. The victim group of cells is read using a second read threshold to obtain a second raw read which includes one or more values. A neighboring read, corresponding to a neighboring group of one or more cells associated with the victim group of cells, is obtained. A composite read is generated, including by selecting from at least the first raw read and the second raw read based at least in part on the neighboring read.

Generation of a composite read based on neighboring data

A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power.

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San Jose, CA, United States of America

Arunkumar Subramanian