Western Digital Technologies, Inc.

Arunkumar Mani

Sharad Kumar Gupta

Arun Kumar Shukla

Silky Mohanty

Athira Kanchiyil

Noor Mohamed

Lakshmi Sowjanya Sunkavelli

A storage system stores data in a primary block and a copy of the data in a secondary block. Parity bits are stored with the data and the copy of the data. A header with logical block information is stored with the copy of the data in the secondary block. The data in the primary block is not stored with a header, which allows more parity bits to be stored with the data in the primary block. This provides more robust error protection for the data stored in the primary block and reduces the need to rely upon the copy of the data in the secondary block.

Storage system and method for avoiding header to improve parity

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a control circuit that controls data to be copied from a single level cell block of a plurality of single level cell blocks to at least two multi level cell blocks of a plurality of multi level cell blocks.

Reusing a cell block for hybrid dual write

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.

Cell block allocation for hybrid dual write

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a grouping circuit that directs a single level writing circuit to write data corresponding to a first logical group to a set of single level cell blocks of a plurality of single level cell blocks. In response to a multi level writing circuit copying data from a set of single level cell blocks to a plurality of multi level cell blocks, a first portion of data from the set of single level cell blocks remains uncopied because the first portion of data is insufficient to fill an entire multi level cell block.

Growing community of inventors

Thirunelveli, India

Arunkumar Mani