Synopsys, Inc.

Synopsis Incorporated

Arunava Saha

Manish Pandey

Per Mattias Bjesse

Sandeep Jana

Pratik Mahajan

Xiaolin C Chen

Alfred Koelbl

Himanshu Jain

Ashvin Mark Dsouza

Jinqing Yu

Jinnan Huang

Chuan Jiang

Ming-Ying Chung

A machine learning model predicts the hardness of unsolved properties. For example, the machine learning model may predict the relative hardness of pairs of properties&#x2014;i.e., which property in the pair is harder to solve. These hardness predictions may then be used to formulate a priority order for a formal verification process to attempt to solve the unsolved properties. As the formal verification process progresses, it generates results. For example, certain properties may be solved. These results are used to update a training set, which is used to further train the machine learning model. The machine learning model is trained at runtime with incremental fine-tuning as the formal verification process progresses.

Estimating hardness of formal properties using on-the-fly machine learning

In one aspect, a fault injection environment and a formal property verification environment are combined in a single integrated flow that allows the user to go back and forth between the two tasks. A system that unifies formal property verification and fault injection includes user interfaces that support the unified use model. In one approach, the FPV tool is the master and its user interface is the primary interface for the user to set up, run and debug faults as well as checkers. This interface allows the user to interactively select the FPV properties and/or the faults to be used for fault analysis. The user interface may provide a view of the faults, for example by listing faults or summarizing faults by class, type, etc.

Efficient mechanism for interactive fault analysis in formal verification environment

The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Efficient mechanism of fault qualification using formal verification

A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.

RTL verification using computational complexity-based property ranking and scheduling

A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved. The stored search path information is also utilized to perform efficient path-influenced search processes when the search-path verification process fails.

Formal verification using cached search path information to verify previously proved/disproved properties

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Sunnyvale, CA, United States of America

Arunava Saha