Intel Corporation

Aruna Kumar L S

Sunil Kumar C R

Sanjib Basu

Anoop Karunan

Prakash K Radhakrishnan

Per E Fornberg

Sleiman Bou-Sleiman

Sunil Kumar Cr

A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

Active state power optimization for high-speed serial input/output interfaces

Embodiments include systems, devices, and methods for a combination CPHY/DPHY/eDP display transmission PHY. A CDE can include a MIPI display serial interface (DSI) circuitry configured to receive 8 bit data compliant with a DSI protocol and output a differential pair signal to a PISO circuit. The same data path is configured for incoming eDP data, which can be routed to circuitry configured to receive 10 bit data compliant with an eDP protocol and output a differential pair signal to a PISO circuit. The system can include a CPHY circuitry that includes a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit having three 7 bit outputs, and CPHY logic to output a trio. The MUX coupled to an output of the PISO is configured to output one of the eDP or the DSI or the CPHY data to an display driver.

Combination circuitry for multiple embedded display transmission protocols

An integrated circuit is described. The integrated circuit includes a display controller having a driver. The display controller is configurable to select two or more display interfaces. The driver is designed to drive respective signals for the two or more display interfaces through a single output.

EDP MIPI DSI combination architecture

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Bengaluru, India

Aruna Kumar L S