Microsoft Technology Licensing, LLC

Intel Corporation

Arun Upadhyaya Kishan

Hari R Pulapaka

Mehmet Iyigun

Landy Wang

Neill Michael Clift

Yevgeniy Bak

David Bradley Probert, Jr

James A Schwartz, Jr

Alain Franck Gefflaut

Ali-Reza Adl-Tabatabai

Gad Shlomo Sheaffer

Koichi Yamada

Jan Stephen Gray

Martin Taillefer

David S Callahan

Ten H Tzen

David Hepkin

Scott Daniel Anderson

David John Linsley

Rene Antonio Vega

Andrew J Ritz

Shira Weinberg

Emily Nicole Wilson

Darek Josip Mihocka

Vadim Bassin

Benjamin Salim Srour

Kevin Michael Broas

Eric J Horvitz

Christopher A Meek

James Morris Alkove

Michael Richard Fortin

Rahul Nair

Alexandre Vicktorovich Grigorovitch

Kirt A Debique

Richard Bruce Ward

Costin Hagiu

Geoffrey T Dunbar

John Andrew Starks

Xin Zhang

Ashwin Palekar

Nelamangal Krishnaswamy Srinivas

Kenneth Dean Johnson

Asela J Gunawardana

Chadd B Knowlton

Ara Bernardi

Jonathan D Schwartz

Jonathan E Lange

Adil Ahmed Sherwani

Sumedh N Barde

Scott A Brender

Vishal Agarwal

Tristan Anthony Brown

Ping Xie

Pedro Miguel Sequeira De Justo Teixeira

Richard K Neves

Nicholas Stephen Judge

Pedro Miguel Teixeira

Ajith Jayamohan

Kinshumann Kinshumann

Youssef M Barakat

Paresh J Maisuria

Neeraj Kumar Singh

Niraj Majmudar

Alex Bendetov

Kenneth M Jung

Thomas Fahrig

Allen Marshall

James Anthony Schwartz, Jr

Yimin Deng

Gurpreet Virdi

John Te-Jui Sheu

Matthew Ryan Miller

Michael H Krause

Gregory John Colombo

Jared Adam Brown

Yau Ning Chin

Terry Jack Mahaffey

Brandon Allsop

Henry Morgan

Garrett Leischner

Richard Allen Pletcher

Ahmad Bilal

Arsalan Ahmad

Michael Grier

Dragos Sambotin

Gopinathan Kannan

Ming Ma

Paul B Koch

Jonathan David Morrison

Kinshuman Kinshumann

Giridharan Sridharan

Pritesh Patwa

M Nashaat Soliman

Reid Joseph Kuhn

Dave M McPherson

Clarence Siu Yeen Dang

Murali Mohan Chintalapati

Sunil P Gottumukkala

Salahuddin Khan

Sai Ganesh Ramachandran

The present disclosure relates to systems, methods, and computer-readable media for determining optimal index configurations for intelligently managing updates of virtual machines in an offline manner in a cloud computing system. For instance, a virtual machine (VM) update system can efficiently determine when to apply updates to virtual machines in an intelligent manner that prevents the updates from interfering with the deallocation of virtual machines. In addition, the VM update system can utilize the operating system (OS) disk image snapshots to automatically provide safeguards and ensure that updates do not degrade the performance of the virtual machines, or in the case of an update failure, that the virtual machines are restored to their previous state without the data loss.

Managing updates on virtual machine systems

Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.

Computer memory management in computing devices

Pooling computing resources based on inferences about a plurality of hardware devices. The method includes identifying inference information about the plurality of devices. The method further includes based on the inference information optimizing resource usage of the plurality of hardware devices.

User presence prediction driven device management

Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.

Widening memory access to an aligned address for unaligned memory operations

During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint. If so, the emulator emits machine code instruction(s) in the second ISA that perform the memory operation using a memory barrier.

Memory ordering annotations for binary emulation

To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Faster access of virtual machine memory backed by a host computing device's virtual memory

One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a hybrid binary, wherein the call is in a format for the guest architecture. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code, an interoperability thunk to handle an incompatibility between the guest architecture and the native architecture, and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk. The method further includes invoking the interoperability thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

Performance optimizations for emulators

Systems, methods, and apparatus for separately loading and managing foreground work and background work of an application. In some embodiments, a method is provided for use by an operating system executing on at least one computer. The operating system may identify at least one foreground component and at least one background component of an application, and may load the at least one foreground component for execution separately from the at least one background component. For example, the operating system may execute the at least one foreground component without executing the at least one background component. In some further embodiments, the operating system may use a specification associated with the application to identify at least one piece of computer executable code implementing the at least one background component.

Decoupling background work and foreground work

Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context. Performance for the unprivileged execution context is substantially unaffected, however, since this memory is mapped as cacheable for the unprivileged execution context.

Speculative side channel attack mitigation using uncacheable memory

A priority-based scheduling and execution of threads may enable the completion of higher-priority tasks above lower-priority tasks. Occasionally, a high-priority thread may request a resource that has already been reserved by a low-priority thread, and the higher-priority thread may be blocked until the low-priority thread relinquishes the reservation. Such prioritization may be acceptable if the low-priority thread is able to execute comparatively unimpeded, but in some scenarios, the low-priority thread may execute at a lower priority than a medium-priority thread that also has a lower priority than the high-priority thread. In this scenario, the medium-priority thread is effectively but incorrectly prioritized above the high-priority thread. Instead, upon detecting this scenario, the device may temporarily elevate the priority of the lower-priority thread over the priority of the medium-priority thread until the lower-priority thread relinquishes the resource, thereby reducing the waiting period of the high-priority thread for the requested resource.

Efficient priority-aware thread scheduling

Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint.

Barrier reduction during code translation

Growing community of inventors

Kirkland, WA, United States of America

Arun Upadhyaya Kishan