Intel Corporation

Intel Ndtm US LLC

Arun Thathachary

Narayanan Ramanan

Shantanu R Rajwade

Tarek Ahmed Ameen Beshari

Matin Amani

Xiang Yang

Krishna Kumar Parat

Richard M Fastow

Han Zhao

An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.

Program verify process having placement aware pre-program verify (PPV) bucket size modulation

Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell

A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

Program verify technique for non-volatile memory

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Santa Clara, CA, United States of America

Arun Thathachary