Advanced Micro Devices Corporation

Yahoo! Inc.

Ati Technologies Ulc

Other

Arun Sundaresan Iyer

Philip Lewis Bohannon

Sathiya Keerthi Selvaraj

Cong Yu

Sriram Sambamurthy

Mridul Muralidharan

Animesh Jain

Vinay Kakade

Alok Baluni

Samuel D Naffziger

Khaled Mammou

Stephen Victor Kosonocky

Gabor Sines

Ihab Amer

Haibo Liu

Aaron Joseph Grenat

Raghu Ramakrishnan

Girish Anathahalli Singrigowda

Sundararajan Sellamanickam

David Mark Ciemiewicz

Nilesh Dalvi

Sudha Thiruvengadam

Bhawna Tomar

Arup Kumar Choudhury

Vipul Agarwal

Prasanth K Vallur

Ashwin Machanavajjhala

Shibashish Patel

Erwin Tam

Mani Abrol

Alok S Kirpal

Nithin Shetty Kidiyoor

Shyam Sundaramoorthy

Ravishankar Karthikeyan

Yousuff Mohammed Shariff

Gregory Sadowski

Krishna Sethupathy Leela

Prashanth Vallur

Shraddha Padiyar

Amit Govil

Tom Gulik

Abhay Deshpande

Prasenjit Sarkar

Various codecs and methods of using the same are disclosed. In one aspect, a method of processing video data is provided that includes encoding or decoding the video data with a codec in aggressive deployment and correcting one or more errors in the encoding or decoding wherein the error correction includes re-encoding or re-decoding the video data in a non-aggressive deployment or generating a skip picture.

Adaptive error-controlled dynamic voltage and frequency scaling for low power video codecs

Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.

Gate oxide soft breakdown detection circuit

Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

Encoding valid data states in source synchronous bus interfaces using clock signal transitions

An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.

Adaptive digital delay line for characterization of clock uncertainties

A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

Low insertion delay clock doubler and integrated circuit clock distribution system using same

A system and method is described for large scale entity-specific classification of each entity-specific set of candidates in a collection of candidates for each specific entity in a collection of entities. The collection of entities may comprise a specific category or domain of entities (e.g. schools, restaurants, manufacturers, products, events, people). Candidates may comprise webpages or other resources with resource identifiers. Entity specific sets of candidates may be found by leveraging search engine query results and user interaction therewith for queries based on entity-specific attributes. The relationship(s) or class(es) for which candidate resources are being classified relative to a specific entity may comprise an authoritative, official home page (OHP), or other class (e.g. fan page, review, aggregator) relative to a specific entity. A feature generator generates entity-specific features for candidates. In accordance with its features, one or more classifiers rank each candidate for a specific class for a specific entity.

Large scale entity-specific resource classification

In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

Self-adjusting clock doubler and integrated circuit clock distribution system using same

Embodiments are directed towards managing a display of search results by employing a query-classification for a search query to selectively display trust search results that are displayed distinct from non-trust search results. A search query is classified into a query-class. A search is then performed over non-trust sources, and selectively over trust data sources to obtain non-trust and trust search results, respectively. The trust search results are rank ordered based on various categories of search criteria, including, for example, explicit and implicit relationships. Based on the query-class, a different number of trust search results may be displayed. Further, a position for which the trust search results may be displayed may be based on the query-class. Moreover, the non-trust search results displayed distinct or separate from the trust search results to readily distinguish a type of source of the search results.

Selectively adding social dimension to web searches

Techniques are provided for the efficient location, processing, and retrieval of local product information derived from web pages generally locatable through form queries submitted to web pages often referred to as the 'deep' or 'hidden' web. In an embodiment, information such as product information and dealer-location information is located on a web page form such as a dealer-locator form. After location of a suitable web page form, editorial wrapping is performed to create an automated information extraction process. Using the automated information extractor, deep-web crawling is performed. A grid-based extraction of individual business records is performed, and matching and ingestion are performed in conjunction with a business listing database. Finally, metadata tags are added to entries in the business listing database. Metadata tags also may be added to entries in other databases.

Method and system for form-filling crawl and associating rich keywords

An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.

Integrated circuit with timing aware clock-tree and method for designing such an integrated circuit

A method and apparatus for designing an integrated circuit to operate at a desired clock frequency range reduces process variation by estimating the value of removable pessimism from a static timing analysis. The pessimism includes, for example, at least one of the removable on-chip-variation (OCV) margin from clock paths, removable OCV margin from data paths, removable IR drop margin from clock paths, and removable interconnects margin. At the timing analysis stage of a design flow, the method and apparatus determines the value of pessimism in the timing critical paths based on timing correlation between adjacent timing critical paths. In response to the determination, the value of pessimism may be reduced in the static timing analysis of the adjacent timing critical paths to optimize the timing performance of the integrated circuit at its desired clock frequency range.

Method and apparatus for designing an integrated circuit

Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter

After receipt of a training and execution plan, a trainer operator is automatically trained based on specified training documents so as to generate a new trained operator for extracting information from documents. The new trained operator is a new version of the trainee operator. Both trainee operators are automatically retained for later use in extracting information from one or more unknown documents. After receipt of the training and execution plan, the new trained operator is automatically executed on one or more unknown documents so as to extract information from such one or more unknown documents.

Apparatus and methods for operator training in information extraction

A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Sequential circuit with dynamic pulse width control

Growing community of inventors

Bengaluru, India

Arun Sundaresan Iyer