Dell Products Inc.

Arun Reddy Chada

Bhyrav M Mutnury

Bhavesh Govindbhai Patel

Han Deng

Jiayi He

Umesh Chandra

Jaydev M Reddy

Mallikarjun Vasa

Vijendera Kumar

ChunLin Liao

An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Inhomogeneous dielectric medium high-speed stripline trace system

Systems and methods provide management of PCIe bandwidth within an IHS (Information Handling System) through predictive evaluation of signaling degradation in PCIe lanes of the IHS. Upon initialization of the IHS, a DPU (Data Processing Unit) generates baseline signal integrity measurements for PCIe links supported by a PCIe interface of the DPU. A signaling analytic model operated by the DPU is calibrated using the baseline signal integrity measurements. A signal degradation prediction is generated by the signaling analytics model. When the signal degradation prediction is confirmed versus observed degradation in the PCIe interface, use of the signaling analytics model is activated. The activated signaling analytics module is then utilized to predict a signaling degradation in a connection supported by the PCIe interface of the DPU. In response to the prediction by the activated signaling analytics model, a corrective operation is initiated in order to prevent the predicted signaling degradation.

Systems and methods for predictive signaling analytics in high-speed data links

Systems and methods are provided for management of PCIe bandwidth within an IHS (Information Handling System). A PCIe connection is detected between a first of the processors of the IHS and a solid-state drive accessed via a DPU (Data Processing Unit). In a processor core of the DPU (e.g., ARM core) buffers are initialized for tracking specific types of errors in the PCIe connection. Upon detecting an error in the PCIe connection, the error is added to one of the designated buffers based on a type of the detected error. If adding of the error in the PCIe connection to the buffer results in a size limit of the buffer being reached, and if the size of the buffer cannot be reduced through retransmission of the errors in the buffer, a transmission speed of the PCIe connection is downgraded, thus extending operations at higher transmission speeds.

Systems and methods for managing high-speed data links

Methods and systems are provided for designing an optimized stack up of layers of a PCB (Printed Circuit Board). A set of constraints is determined for the PCB stack up, where the constraints limit a total number of layers, a number of signal layers, and a thickness of the PCB stack up. Each of the constraints on the PCB stack up is encoded as an equality or an inequality. The set of equalities and inequalities is solved using integer programming techniques to identify an optimal solution to the set of constraints on the PCB stack up, where the optimal solution specifies an arrangement of signaling layers for the PCB. An estimate is generated for impedances and losses for the optimal PCB stack up. The constraints on a PCB stack up are modified when the estimated impedances and losses for the optimal PCB stack up are above a target threshold.

Systems and methods for generating PCB (printed circuit board) designs

An information handling system includes a transmitter that transmits data over a channel to a receiver. The transmitter operates to transmit a test sequence including a repeating sequence of a number of logic 1's and the number of logic 0's. The receiver operates to detect noise injected onto the channel based upon an output from a data eye sampler in response to the test sequence.

In situ common-mode noise measurement in high-speed data communication interfaces

A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.

Printed circuit board having vias arranged for high speed serial differential pair data links

A serial data channel includes a transmitter that encodes serial data using a quaternary PAM-4 scheme, wherein the four PAM-4 signal levels include two balanced pairs of differential signal levels. The channel includes a de-emphasis circuit that determines that first and second symbols are in a first PAM-4 state, that a third symbol is in a second PAM-4 state, and provides a first de-emphasis to a voltage level of the second symbol in response to determining that the third symbol is represented as the second state. The de-emphasis circuit further determines that fourth and fifth symbols are in the second state, that a sixth symbol is in the first state, and provides a second de-emphasis to a voltage level of the fifth symbol in response to determining that the sixth symbol is represented as the first state. The first de-emphasis and the second de-emphasis represent different de-emphasis levels.

System and method for PAM-4 transmitter bit equalization for improved channel performance beyond 32 Gbps

An information handling system communicates information across a physical link with high and low signal values sent at a unit interval. Feed forward equalization improves signal transfer with pre-emphasis of low-to-high signals and de-emphasis of high-to-low signals lasting for a fraction of the unit interval, such as one-half or one-quarter of the unit interval. Fractional unit interval pre-emphasis and de-emphasis reduce inter symbol interference to improve frequency domain eye structure at the physical link receiver.

Information handling system half unit interval equalization

A high-speed serial data interface includes a transmitter and a receiver. The transmitter includes a feed-forward equalization (FFE) module. The FFE module has a main tap and at least one secondary tap. In a first mode, a sum of absolute values of a main tap compensation value and a secondary tap compensation value of each one of the at least one secondary tap is equal to one. In a second mode, the main tap compensation value has a unity gain equal to one, and each secondary tap compensation value is greater than or equal to the secondary tap compensation value in the first mode divided by the main tap compensation value in the first mode.

System and method to enhance feed-forward equalization in a high-speed serial interface

A method includes providing a first circuit trace and a second circuit trace on a printed circuit board, determining a far end cross-talk (FEXT) response associated with the first circuit trace, determining a time delay associated with the second circuit trace, estimating a floquet response associated with the time delay, comparing the FEXT response with an interface frequency associated with the first circuit trace, comparing the floquet response with the interface frequency, and determining whether the floquet response cancels the FEXT response on the first circuit trace at the interface frequency.

System and method of cancelling floquet mode resonance and far end crosstalk, and mitigating crosstalk in a printed circuit board

A PAM equalization optimization system includes a BIOS coupled to a PAM engine and an equalization engine. The BIOS determines an effective equalization tap number of equalization taps that each provide an equalization result above a predetermined amount. The BIOS then determines whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number of equalization taps that are available for equalizing a signal. When the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-symbol equalization on signals modulated using the PAM engine. When the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-bit equalization on signals modulated using the PAM engine.

Pulse amplitude modulation equalization optimization system

A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as where fis the floquet frequency, and tis the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.

System and method of determining high speed resonance due to coupling from broadside layers

A method includes receiving a serial data stream at a transmitter of a serial channel, encoding the serial data stream using a quaternary pulse amplitude modulation (PAM-4) scheme into a stream of 2-bit symbols, wherein a particular symbol is represented as a signal at one of four signal levels provided for a unit interval of time, determining that a first symbol of the encoded serial data stream is represented as a highest state of the PAM-4 scheme, and, in response, providing a first output signal on an output of the transmitter, wherein the first output signal includes a first portion at a first voltage level associated with the highest state for a first half of a first unit interval of time associated with the first symbol, followed by a second portion at a second voltage level associated with a de-emphasized highest state of the PAM-4 scheme for a second half of the first unit interval of time.

System and method for PAM-4 transmitter bit equalization for improved channel performance

A serial data channel includes a transmitter that encodes data using a PAM-4 where each symbol is represented by one of four signal levels comprising two balanced pairs of differential signal levels, and a de-emphasis circuit. The circuit determines that a symbol represents as a first instance of a first signal state, determines that a next symbol represents a second instance of the first state, and determines that a third symbol is represented as a second state. The circuit determines that the second state is of a same balanced pair as the first state and, in response, provides a de-emphasis to the second symbol. The circuit determines that the second state is of a different balanced pair as the first state and, in response, provides the de-emphasis and a correction factor to the second symbol.

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Round Rock, TX, United States of America

Arun Reddy Chada