Qualcomm Incorporated

Arun Raghupathy

Raghu Narayan Challa

Brian Clarke Banister

Tao Li

Inyup Kang

Matthew Levi Severson

Steven C Ciccarelli

Paul E Peterzell

Gilbert Christopher Sih

Brett Christopher Walker

Christian Holenstein

Robert Reeves

Nagabhushana T Sindhushayana

Gurkanwal Singh Sahota

Prasad S Gudem

Puay Hoe See

Soon-Seng Lau

Brian George

Injup Kang

Steven C c/o Qualcomm Incorporated Ciccarelli

Techniques for controlling operation of control loops in a receiver are described. The operation of at least one control loop is modified in conjunction with a change in operating state, which may correspond to a change in linearity state, gain state, operating frequency, antenna configuration, etc. A change in linearity state may occur when jammers are detected and may cause bias current of analog circuit blocks to be adjusted. The at least one control loop to be modified may include a DC loop, an AGC loop, etc. The operation of a control loop may be modified by disabling the control loop or changing its time constant prior to changing operating state, waiting a predetermined amount of time to allow the receiver to settle, and enabling the control loop or restoring its time constant after waiting the predetermined amount of time.

Techniques for controlling operation of control loops in a receiver

A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Direct conversion receiver architecture

A technique for noise reduction in a wireless communication system uses controllable bandwidth filters () to filter a received signal. In a typical implementation, the filters () are used at baseband frequencies. A measurement (RSSI) is indicative of the strength of the received signal. A control circuit () generates a control signal () to control the bandwidth of the filters (). If the received signal strength is above a first threshold, a wider bandwidth may be used for the filters (). If the received signal is below a second threshold, the control circuit () generates the control signal () to set the filters () to a more narrow bandwidth. The system () may also be used with digital filters () following digitization by analog to digital converters (ADCs) (). The system () is particularly well-suited for operation with noise-shaped ADCs (), such as Delta-Sigma converters.

Noise reduction filtering in a wireless communication system

Methods and apparatus for amplifier AM and PM predistortion and autocalibration. AM and PM amplifier distortion can be corrected using predistortion. The AM and PM distortion characteristics of the amplifier are determined using an autocalibration technique. The amplifier characteristics can be stored in distinct look up tables. Alternatively, the inverse of the amplifier characteristics can be stored in distinct look up tables. Signals that are to be amplified are characterized in polar format having a phase component with a normalized magnitude and a magnitude component. The phase component can be predistorted by applying the inverse of the PM distortion characteristics to the signal. Similarly, the magnitude component can be predistorted by applying the inverse of the AM distortion characteristics to the signal. The predistorted phase component can be amplified using the previously characterized amplifier. The predistorted magnitude component can be used to set the gain of the previously characterized amplifier.

Amplifier predistortion and autocalibration method and apparatus

Variable gain selection in direct conversion receiver

An AMPS receiver system utilizing a ZIF architecture and processing received forward link signals in the digital domain. The AMPS receiver system includes an antenna (), a direct converter (), high dynamic A/D converters (), low pass filters (), a phase shifter (), a digital VGA (), a digital FM demodulator (), an accumulator () and a controller (). The direct converter () further includes a low noise amplifier (), a splitter (), mixers () and low pass filters (). The controller () adjusts the gains of the low noise amplifier () and the digital VGA () based on the average power of the signal outputted by the digital VGA ().

AMPS receiver using a zero-IF architecture

In one embodiment, the invention is directed toward techniques for generating results in a logarithmic domain. The techniques may exploit properties of a logarithmic function to reduce the memory requirements needed to implement lookup tables. For example, the techniques may utilize non-uniform sampling over a logarithmic or logarithmic-like function to reduce the number of entries needed for a given lookup table. In particular, the techniques may involve separating a number into an exponent component and a mantissa component. Each of these different components can then be converted from a first domain to a second domain using different lookup tables.

Logarithmic lookup tables

A compensation circuit to correct for mismatch in a quadrature receiver comprises first and second mixers to receive a radio frequency (RF) modulated signal. One mixer receives an I local oscillator signal while the second mixer receives a Q local oscillator signal wherein the I and Q local oscillators have frequencies that are substantially identical. The output of the first and second mixers are coupled to first and second filters, respectively, which generate the I and Q output signals, respectively. Inherent circuit mismatch generate gain and/or phase errors that result in mismatch in the I and Q output signals. A correction circuit automatically applies a correction factor to at least one of the I and Q output signals to correct the gain and/or phase error by applying a multiplication factor to at least one of the I and Q output signals to thereby generate a corrected signal. The correction factors must be determined on a unit by unit basis. Testing in the final stages of factory assembly may be used to determine the value of the correction factor. The correction factor may be stored in a memory of the wireless communication device and used thereafter.

System and method for I-Q mismatch compensation in a low IF or zero IF receiver

A method and device for converting at least one narrow band RF signal, being suitable for transmission between at least one communications device suitable for receiving wide-band RF signals and at least one base station, to baseband. The method includes directly down-converting a signal spectrum including the at least one RF narrow-band signal to baseband such that the at least one narrow-band RF signal results at a low intermediate frequency (IF). And, digitally phase rotating the down-converted signal spectrum such that the at least one narrow-band RF signal is phase rotated from the low-IF to baseband.

Growing community of inventors

San Diego, CA, United States of America

Arun Raghupathy