Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Arun Radhakrishnan

Karthik Sundaram

Edward A Brekelbaum

Sushant Kondguli

Kevin Michael Lepak

David Conrad Tannenbaum

Benjamin T Sander

Michael T Clark

Kelvin Domnic Goveas

Michael A Filippo

David Edward Kroesche

Karthikeyan Muthusamy

Rama S Gopal

Murali S Chinnakonda

Brian C Grayson

Wilson Wai Lun Fung

Zhenhong Liu

Zachary Neyland

Wayne Yamamoto

Anshujit Sharma

A graphics processing unit (GPU) includes a table located in a memory of the GPU and a cache hierarchy. The table contains an address of inactive data in a cache hierarchy of the GPU in which the inactive data is associated with an intermediate render target. The cache hierarchy is responsive to an eviction event by discarding the inactive data from the cache hierarchy without performing a writeback to a system memory associated with the GPU based on the address of the inactive data being contained in the table. The cache hierarchy may obtain the address of the inactive data from the table, and the inactive data may be located in a last-level cache of the cache hierarchy. In one embodiment, the address of inactive data in a cache hierarchy of the GPU includes a range of addresses for the inactive data.

Systems, methods, and devices for discarding inactive intermediate render targets

A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

Methods and apparatus for implementing cache policies in a graphics processing unit

Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.

Spatial memory streaming confidence mechanism

Apparatuses, systems, methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, an SMS prefetch engine uses trigger-to-trigger stride detection to promote training table entries to pattern history table (PHT) entries and to drive spatially related prefetches in more distant regions. In another aspect, an SMS prefetch engine maintains a blacklist of program counter (PC) values to not use as trigger values. In yet another aspect, an SMS prefetch engine uses hashed values of certain fields, such as the trigger PC, in entries of, e.g., filter tables, training tables, and PHTs, as index values for the table.

System and method for spatial memory streaming training

A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

Address re-ordering mechanism for efficient pre-fetch training in an out-of order processor

According to one general aspect, a method may include monitoring a plurality of pre-fetch cache requests associated with a data stream. The method may also include evaluating an accuracy of the pre-fetch cache requests. The method may further include, based at least in part upon the accuracy of the pre-fetch cache requests, adjusting a maximum amount of data that is allowably pre-fetched in excess of a data stream's current actual demand for data.

Adaptive mechanism to tune the degree of pre-fetches streams

According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.

Pre-fetch chaining

A computing system includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction in an out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

Address re-ordering mechanism for efficient pre-fetch training in an out-of-order processor

A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.

Controlling writes to non-renamed register space in an out-of-order execution microprocessor

A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop of microcode instructions forming a microcode sequence. The microcode sequence is stored within a storage of a microcode unit. The method also includes storing a loop count value associated with the repetitive microcode instruction to a sequence control unit of the microcode unit. The method further includes determining a number of iterations to issue the microcode sequence for execution by an instruction pipeline based upon the loop count value. In response to receiving the repetitive microcode instruction, the method includes continuously issuing the microcode sequence for the number of iterations.

Method for optimizing loop control of microcoded instructions

A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is coupled to receive the floating point operation for execution, and is configured to detect a misprediction of the execution latency. In some embodiments, an exception may be taken in response to the misprediction. In other embodiments, the floating point operation may be rescheduled with the corrected execution latency.

Growing community of inventors

Austin, TX, United States of America

Arun Radhakrishnan