Texas Instruments Corporation

Other

Arun Kumar Mohan

Neeraj Shrivastava

Ani Xavier

Jagannathan Venkataraman

Shagun Dusad

Aravind Ganesan

Nagalinga Swamy Basayya Aremallapur

Sai Aditya Krishnaswamy Nurani

Rakesh Chikkanayakanahalli Manjunath

Harshavardhan Adepu

Naveen Kv

Venkatesh Doreswamy

Chetan P Hanakanahalli

Gehesh Edakkuttathil Muhammed

Medha Yogish Rao

Jolly Anil John

Aviral Singhal

Surendra Rao Shankapal

Dakshath P Jembige

Nagaraja Basavaraja Setty

An example apparatus includes: first voltage-to-delay circuitry having an output; second voltage-to-delay circuitry having an output; time domain converter circuitry having a first input, a trim input, and an output, the first input of the time domain converter circuitry coupled to the first voltage-to-delay circuitry; comparator circuitry having a first input, a second input, and an output, the first input of the comparator circuitry coupled to the output of the first voltage-to-delay circuitry and the first input of the time domain converter circuitry, the second input of the comparator circuitry coupled to the output of the second voltage-to-delay circuitry; and trim circuitry having a first input, a second input, and an output, the first input of the trim circuitry coupled to the output of the time domain converter circuitry, the second input of the trim circuitry coupled to the output of the comparator circuitry.

Methods and apparatus to calibrate analog-to-digital converters

A circuit includes first, second, third, and fourth transistors, and a capacitor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, second terminal, and a control terminal. The capacitor has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor has a first terminal coupled to the first terminal of the second transistor, a second terminal, and a control terminal coupled to the control terminal of the first transistor. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the third transistor, and a control terminal coupled to the control terminal of the second transistor.

Pretap equalizable continuous time linear equalizer

A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Offset correction in high-speed serial link receivers

A non-invasive female urine collection device comprising a first pipe with an inflatable balloon attached to a first end of the first pipe; and a urine collection member attached to a second end of the first pipe such that, when the first end of the first pipe is inserted into vagina, the urine collection member covers urethra for collecting the urine discharged through the urethra. The urine collection member further comprising a first membrane and a second membrane together forming a urine collection pouch, in that the second membrane is shorter than the first membrane exposing the first membrane around Urethra for collecting the urine discharged through the urethra. The urine collection member further comprising a set of spikes formed on the first membrane in line with the urethra to prevent splashing of urine coming out of urethra.

Device, system and apparatus for female urine collection

A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

Top plate sampling analog-to-digital converter (ADC) with residue amplifier non-linearity reduction

An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

Pipelined analog-to-digital converter

In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

Top plate sampling circuit including input-dependent dual clock boost circuits

In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

Negative capacitance circuits including temperature-compensation biasings

The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.

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Bengaluru, India

Arun Kumar Mohan