Cadence Design Systems, Inc.

Arun Kumar Mishra

Igor Keller

Praveen Ghanta

Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

Systems and methods for statistical static timing analysis

Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.

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Noida, India

Arun Kumar Mishra